defineGateSize "SRAM2RW64x4" "A2[5]" '(0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW64x4" "A2[5]" '(
("M1" 0.021 0.96757 0 0 0.96757 0 0)
("M2" 0.021 0.1516 46.0717 0 0.1516 0 0)
("M3" 0.021 0.1516 53.2873 0 0.1516 0 0)
("M4" 0.021 0.1516 60.5023 0 0.1516 0 0)
("M5" 0.021 0.1516 67.7169 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x4" "A1[5]" '(0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW64x4" "A1[5]" '(
("M1" 0.021 0.97597 0 0 0.97597 0 0)
("M2" 0.021 0.1516 46.4717 0 0.1516 0 0)
("M3" 0.021 0.1516 53.6872 0 0.1516 0 0)
("M4" 0.021 0.1516 60.9022 0 0.1516 0 0)
("M5" 0.021 0.1516 68.1168 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x4" "OEB1" '(0 0.081 0.081 0.081 0.081 0.081 0.081 0.081 0.081 0.081)
defineHierAntennaProp "SRAM2RW64x4" "OEB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.081 0.5956 0.96601 0 0.5956 0 0)
("M3" 0.081 0.1516 8.31855 0 0.1516 0 0)
("M4" 0.081 0.1516 10.1895 0 0.1516 0 0)
("M5" 0.081 0.1516 12.0603 0 0.1516 0 0)
("M6" 0.081 0 0 0 0 0 0)
("M7" 0.081 0 0 0 0 0 0)
("M8" 0.081 0 0 0 0 0 0)
("M9" 0.081 0 0 0 0 0 0)
("MRDL" 0.081 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x4" "OEB2" '(0 0.081 0.081 0.081 0.081 0.081 0.081 0.081 0.081 0.081)
defineHierAntennaProp "SRAM2RW64x4" "OEB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.081 0.58978 0.966009 0 0.58978 0 0)
("M3" 0.081 0.1516 8.24671 0 0.1516 0 0)
("M4" 0.081 0.1516 10.1176 0 0.1516 0 0)
("M5" 0.081 0.1516 11.9885 0 0.1516 0 0)
("M6" 0.081 0 0 0 0 0 0)
("M7" 0.081 0 0 0 0 0 0)
("M8" 0.081 0 0 0 0 0 0)
("M9" 0.081 0 0 0 0 0 0)
("MRDL" 0.081 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x4" "WEB1" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineHierAntennaProp "SRAM2RW64x4" "WEB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1461 1.5667 1.03833 0 1.5667 0 0)
("M3" 0.1461 0.1516 11.761 0 0.1516 0 0)
("M4" 0.1461 0.1516 12.7978 0 0.1516 0 0)
("M5" 0.1461 0.1516 13.8346 0 0.1516 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x4" "A2[4]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM2RW64x4" "A2[4]" '(
("M1" 0.0366 0.811118 0 0 0.811118 0 0)
("M2" 0.0366 0.1516 22.1602 0 0.1516 0 0)
("M3" 0.0366 0.1516 26.3006 0 0.1516 0 0)
("M4" 0.0366 0.1516 30.4406 0 0.1516 0 0)
("M5" 0.0366 0.1516 34.5804 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x4" "CE2" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineHierAntennaProp "SRAM2RW64x4" "CE2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0342 0.28354 4.11185 0 0.28354 0 0)
("M5" 0.0342 0.1516 12.4017 0 0.1516 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x4" "CSB2" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM2RW64x4" "CSB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0366 0.39604 1.83562 0 0.39604 0 0)
("M5" 0.0366 0.1516 12.6556 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x4" "O2[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x4" "O2[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.284293 0 0 0.284293 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x4" "I2[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW64x4" "I2[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.29448 1.24826 0 1.29448 0 0)
("M4" 0.021 0.1516 62.886 0 0.1516 0 0)
("M5" 0.021 0.1516 70.1004 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x4" "I2[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW64x4" "I2[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.29448 1.24826 0 1.29448 0 0)
("M4" 0.021 0.1516 62.886 0 0.1516 0 0)
("M5" 0.021 0.1516 70.1004 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x4" "O2[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x4" "O2[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.280633 0 0 0.280633 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x4" "O2[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x4" "O2[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.281233 0 0 0.281233 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x4" "I2[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x4" "I2[1]" '(0.6)
defineHierAntennaProp "SRAM2RW64x4" "I2[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.29448 1.24826 0 1.29448 0 0)
("M4" 0.021 0.1516 62.886 0 0.1516 0 0)
("M5" 0.021 0.1516 70.1004 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x4" "I2[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x4" "I2[0]" '(0.6)
defineHierAntennaProp "SRAM2RW64x4" "I2[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.29448 1.24826 0 1.29448 0 0)
("M4" 0.021 0.1516 62.886 0 0.1516 0 0)
("M5" 0.021 0.1516 70.1004 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x4" "O2[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x4" "O2[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.279253 0 0 0.279253 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x4" "I1[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x4" "I1[2]" '(0.6)
defineHierAntennaProp "SRAM2RW64x4" "I1[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.29448 1.24826 0 1.29448 0 0)
("M4" 0.021 0.1516 62.886 0 0.1516 0 0)
("M5" 0.021 0.1516 70.1004 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x4" "O1[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x4" "O1[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271813 0 0 0.271813 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x4" "I1[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x4" "I1[3]" '(0.6)
defineHierAntennaProp "SRAM2RW64x4" "I1[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.29448 1.24826 0 1.29448 0 0)
("M4" 0.021 0.1516 62.886 0 0.1516 0 0)
("M5" 0.021 0.1516 70.1004 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x4" "O1[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x4" "O1[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.272173 0 0 0.272173 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x4" "O1[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x4" "O1[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.288913 0 0 0.288913 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x4" "I1[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x4" "I1[1]" '(0.6)
defineHierAntennaProp "SRAM2RW64x4" "I1[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.29448 1.24826 0 1.29448 0 0)
("M4" 0.021 0.1516 62.886 0 0.1516 0 0)
("M5" 0.021 0.1516 70.1004 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x4" "I1[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x4" "I1[0]" '(0.6)
defineHierAntennaProp "SRAM2RW64x4" "I1[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.29448 1.24826 0 1.29448 0 0)
("M4" 0.021 0.1516 62.886 0 0.1516 0 0)
("M5" 0.021 0.1516 70.1004 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x4" "O1[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x4" "O1[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.276973 0 0 0.276973 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x4" "A1[4]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW64x4" "A1[4]" '(0.6)
defineHierAntennaProp "SRAM2RW64x4" "A1[4]" '(
("M1" 0.0366 0.819518 0 0 0.819518 0 0)
("M2" 0.0366 0.1516 22.3897 0 0.1516 0 0)
("M3" 0.0366 0.1516 26.5301 0 0.1516 0 0)
("M4" 0.0366 0.1516 30.6701 0 0.1516 0 0)
("M5" 0.0366 0.1516 34.8099 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x4" "A1[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW64x4" "A1[1]" '(0.6)
defineHierAntennaProp "SRAM2RW64x4" "A1[1]" '(
("M1" 0.0366 0.819518 0 0 0.819518 0 0)
("M2" 0.0366 0.1516 22.3897 0 0.1516 0 0)
("M3" 0.0366 0.1516 26.5301 0 0.1516 0 0)
("M4" 0.0366 0.1516 30.6701 0 0.1516 0 0)
("M5" 0.0366 0.1516 34.8099 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x4" "A1[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW64x4" "A1[2]" '(0.6)
defineHierAntennaProp "SRAM2RW64x4" "A1[2]" '(
("M1" 0.0366 0.819518 0 0 0.819518 0 0)
("M2" 0.0366 0.1516 22.3897 0 0.1516 0 0)
("M3" 0.0366 0.1516 26.5301 0 0.1516 0 0)
("M4" 0.0366 0.1516 30.6701 0 0.1516 0 0)
("M5" 0.0366 0.1516 34.8099 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x4" "A1[3]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW64x4" "A1[3]" '(0.6)
defineHierAntennaProp "SRAM2RW64x4" "A1[3]" '(
("M1" 0.0366 0.819518 0 0 0.819518 0 0)
("M2" 0.0366 0.1516 22.3897 0 0.1516 0 0)
("M3" 0.0366 0.1516 26.5301 0 0.1516 0 0)
("M4" 0.0366 0.1516 30.6701 0 0.1516 0 0)
("M5" 0.0366 0.1516 34.8099 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x4" "A1[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW64x4" "A1[0]" '(0.6)
defineHierAntennaProp "SRAM2RW64x4" "A1[0]" '(
("M1" 0.0366 0.819518 0 0 0.819518 0 0)
("M2" 0.0366 0.1516 22.3897 0 0.1516 0 0)
("M3" 0.0366 0.1516 26.5301 0 0.1516 0 0)
("M4" 0.0366 0.1516 30.6701 0 0.1516 0 0)
("M5" 0.0366 0.1516 34.8099 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x4" "A2[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW64x4" "A2[0]" '(0.6)
defineHierAntennaProp "SRAM2RW64x4" "A2[0]" '(
("M1" 0.0366 0.811118 0 0 0.811118 0 0)
("M2" 0.0366 0.1516 22.1602 0 0.1516 0 0)
("M3" 0.0366 0.1516 26.3006 0 0.1516 0 0)
("M4" 0.0366 0.1516 30.4406 0 0.1516 0 0)
("M5" 0.0366 0.1516 34.5804 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x4" "A2[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW64x4" "A2[1]" '(0.6)
defineHierAntennaProp "SRAM2RW64x4" "A2[1]" '(
("M1" 0.0366 0.811118 0 0 0.811118 0 0)
("M2" 0.0366 0.1516 22.1602 0 0.1516 0 0)
("M3" 0.0366 0.1516 26.3006 0 0.1516 0 0)
("M4" 0.0366 0.1516 30.4406 0 0.1516 0 0)
("M5" 0.0366 0.1516 34.5804 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x4" "A2[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW64x4" "A2[2]" '(0.6)
defineHierAntennaProp "SRAM2RW64x4" "A2[2]" '(
("M1" 0.0366 0.811118 0 0 0.811118 0 0)
("M2" 0.0366 0.1516 22.1602 0 0.1516 0 0)
("M3" 0.0366 0.1516 26.3006 0 0.1516 0 0)
("M4" 0.0366 0.1516 30.4406 0 0.1516 0 0)
("M5" 0.0366 0.1516 34.5804 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x4" "A2[3]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW64x4" "A2[3]" '(0.6)
defineHierAntennaProp "SRAM2RW64x4" "A2[3]" '(
("M1" 0.0366 0.811118 0 0 0.811118 0 0)
("M2" 0.0366 0.1516 22.1602 0 0.1516 0 0)
("M3" 0.0366 0.1516 26.3006 0 0.1516 0 0)
("M4" 0.0366 0.1516 30.4406 0 0.1516 0 0)
("M5" 0.0366 0.1516 34.5804 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x4" "CE1" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineDiodeProtection "SRAM2RW64x4" "CE1" '(0.6)
defineHierAntennaProp "SRAM2RW64x4" "CE1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0342 0.2917 3.93276 0 0.2917 0 0)
("M5" 0.0342 0.1516 12.4612 0 0.1516 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x4" "CSB1" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW64x4" "CSB1" '(0.6)
defineHierAntennaProp "SRAM2RW64x4" "CSB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0366 0.40618 1.93503 0 0.40618 0 0)
("M5" 0.0366 0.1516 13.032 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x4" "WEB2" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineDiodeProtection "SRAM2RW64x4" "WEB2" '(0.6)
defineHierAntennaProp "SRAM2RW64x4" "WEB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1461 1.55662 1.03834 0 1.55662 0 0)
("M3" 0.1461 0.1516 11.692 0 0.1516 0 0)
("M4" 0.1461 0.1516 12.7289 0 0.1516 0 0)
("M5" 0.1461 0.1516 13.7656 0 0.1516 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x4" "VDD" '(0 0 0 0 3.0816 3.0816 3.0816 3.0816 3.0816 3.0816)
defineDiodeProtection "SRAM2RW64x4" "VDD" '(0 0 0 0 89.05071 89.05071 89.05071 89.05071 89.05071 89.05071)
defineHierAntennaProp "SRAM2RW64x4" "VDD" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 3.0816 1396.92 29.0975 0 1396.92 0 0)
("M6" 3.0816 0 0 0 0 0 0)
("M7" 3.0816 0 0 0 0 0 0)
("M8" 3.0816 0 0 0 0 0 0)
("M9" 3.0816 0 0 0 0 0 0)
("MRDL" 3.0816 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x4" "VSS" '(0 0 0 0 5.49 5.49 5.49 5.49 5.49 5.49)
defineDiodeProtection "SRAM2RW64x4" "VSS" '(0 0 0 0 75.01306 75.01306 75.01306 75.01306 75.01306 75.01306)
defineHierAntennaProp "SRAM2RW64x4" "VSS" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 5.49 1396.95 86.3142 0 1396.95 0 0)
("M6" 5.49 0 0 0 0 0 0)
("M7" 5.49 0 0 0 0 0 0)
("M8" 5.49 0 0 0 0 0 0)
("M9" 5.49 0 0 0 0 0 0)
("MRDL" 5.49 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x8" "O1[5]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x8" "O1[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.26188 0 0 0.26188 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x8" "O2[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x8" "O2[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.26188 0 0 0.26188 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x8" "WEB2" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineHierAntennaProp "SRAM2RW64x8" "WEB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1461 1.56742 1.03833 0 1.56742 0 0)
("M3" 0.1461 0.1516 11.766 0 0.1516 0 0)
("M4" 0.1461 0.1516 12.8028 0 0.1516 0 0)
("M5" 0.1461 0.1516 13.8395 0 0.1516 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x8" "OEB2" '(0 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434)
defineHierAntennaProp "SRAM2RW64x8" "OEB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1434 0.90928 0.966015 0 0.90928 0 0)
("M3" 0.1434 0.1516 7.3064 0 0.1516 0 0)
("M4" 0.1434 0.1516 8.36303 0 0.1516 0 0)
("M5" 0.1434 0.1516 9.41959 0 0.1516 0 0)
("M6" 0.1434 0 0 0 0 0 0)
("M7" 0.1434 0 0 0 0 0 0)
("M8" 0.1434 0 0 0 0 0 0)
("M9" 0.1434 0 0 0 0 0 0)
("MRDL" 0.1434 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x8" "OEB1" '(0 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434)
defineHierAntennaProp "SRAM2RW64x8" "OEB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1434 0.9151 0.966016 0 0.9151 0 0)
("M3" 0.1434 0.1516 7.34698 0 0.1516 0 0)
("M4" 0.1434 0.1516 8.40361 0 0.1516 0 0)
("M5" 0.1434 0.1516 9.46017 0 0.1516 0 0)
("M6" 0.1434 0 0 0 0 0 0)
("M7" 0.1434 0 0 0 0 0 0)
("M8" 0.1434 0 0 0 0 0 0)
("M9" 0.1434 0 0 0 0 0 0)
("MRDL" 0.1434 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x8" "WEB1" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineHierAntennaProp "SRAM2RW64x8" "WEB1" '(
("M1" 0 0.15352 0 0 0.15352 0 0)
("M2" 0.1461 1.56742 1.03833 0 1.56742 0 0)
("M3" 0.1461 0.15352 11.766 0 0.15352 0 0)
("M4" 0.1461 0.15352 12.8159 0 0.15352 0 0)
("M5" 0.1461 0.15352 13.8658 0 0.15352 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x8" "I1[7]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW64x8" "I1[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28566 1.24827 0 1.28566 0 0)
("M4" 0.021 0.1516 62.4661 0 0.1516 0 0)
("M5" 0.021 0.1516 69.6805 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x8" "O1[7]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x8" "O1[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.26188 0 0 0.26188 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x8" "O2[5]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x8" "O2[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.26188 0 0 0.26188 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x8" "O1[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x8" "O1[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.26188 0 0 0.26188 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x8" "I2[5]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW64x8" "I2[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28566 1.24827 0 1.28566 0 0)
("M4" 0.021 0.1516 62.4661 0 0.1516 0 0)
("M5" 0.021 0.1516 69.6805 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x8" "O2[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x8" "O2[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.26188 0 0 0.26188 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x8" "O2[4]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x8" "O2[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.26188 0 0 0.26188 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x8" "I2[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x8" "I2[2]" '(0.6)
defineHierAntennaProp "SRAM2RW64x8" "I2[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28566 1.24827 0 1.28566 0 0)
("M4" 0.021 0.1516 62.4661 0 0.1516 0 0)
("M5" 0.021 0.1516 69.6805 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x8" "I2[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x8" "I2[3]" '(0.6)
defineHierAntennaProp "SRAM2RW64x8" "I2[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28566 1.24827 0 1.28566 0 0)
("M4" 0.021 0.1516 62.4661 0 0.1516 0 0)
("M5" 0.021 0.1516 69.6805 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x8" "O2[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x8" "O2[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.26188 0 0 0.26188 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x8" "O2[6]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x8" "O2[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.26188 0 0 0.26188 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x8" "I2[6]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x8" "I2[6]" '(0.6)
defineHierAntennaProp "SRAM2RW64x8" "I2[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28566 1.24827 0 1.28566 0 0)
("M4" 0.021 0.1516 62.4661 0 0.1516 0 0)
("M5" 0.021 0.1516 69.6805 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x8" "I2[4]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x8" "I2[4]" '(0.6)
defineHierAntennaProp "SRAM2RW64x8" "I2[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28566 1.24827 0 1.28566 0 0)
("M4" 0.021 0.1516 62.4661 0 0.1516 0 0)
("M5" 0.021 0.1516 69.6805 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x8" "I2[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x8" "I2[1]" '(0.6)
defineHierAntennaProp "SRAM2RW64x8" "I2[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28566 1.24827 0 1.28566 0 0)
("M4" 0.021 0.1516 62.4661 0 0.1516 0 0)
("M5" 0.021 0.1516 69.6805 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x8" "O2[7]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x8" "O2[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.26188 0 0 0.26188 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x8" "I2[7]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x8" "I2[7]" '(0.6)
defineHierAntennaProp "SRAM2RW64x8" "I2[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28566 1.24827 0 1.28566 0 0)
("M4" 0.021 0.1516 62.4661 0 0.1516 0 0)
("M5" 0.021 0.1516 69.6805 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x8" "I2[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x8" "I2[0]" '(0.6)
defineHierAntennaProp "SRAM2RW64x8" "I2[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28566 1.24827 0 1.28566 0 0)
("M4" 0.021 0.1516 62.4661 0 0.1516 0 0)
("M5" 0.021 0.1516 69.6805 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x8" "O2[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x8" "O2[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.26188 0 0 0.26188 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x8" "CE2" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineDiodeProtection "SRAM2RW64x8" "CE2" '(0.6)
defineHierAntennaProp "SRAM2RW64x8" "CE2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0342 0.30916 3.47688 0 0.30916 0 0)
("M5" 0.0342 0.1516 12.5158 0 0.1516 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x8" "A2[5]" '(0 0 0 0 5.49 5.49 5.49 5.49 5.49 5.49)
defineDiodeProtection "SRAM2RW64x8" "A2[5]" '(0.6)
defineHierAntennaProp "SRAM2RW64x8" "A2[5]" '(
("M1" 0 1.32779 0 0 1.32779 0 0)
("M2" 0 0.1726 0 0 0.1726 0 0)
("M3" 0 0.1726 0 0 0.1726 0 0)
("M4" 0 1.7026 0 0 1.7026 0 0)
("M5" 5.49 1727.31 86.3176 0 1727.31 0 0)
("M6" 5.49 0 0 0 0 0 0)
("M7" 5.49 0 0 0 0 0 0)
("M8" 5.49 0 0 0 0 0 0)
("M9" 5.49 0 0 0 0 0 0)
("MRDL" 5.49 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x8" "A2[4]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW64x8" "A2[4]" '(0.6)
defineHierAntennaProp "SRAM2RW64x8" "A2[4]" '(
("M1" 0.0366 0.820118 0 0 0.820118 0 0)
("M2" 0.0366 0.1516 22.4061 0 0.1516 0 0)
("M3" 0.0366 0.1516 26.5464 0 0.1516 0 0)
("M4" 0.0366 0.1516 30.6865 0 0.1516 0 0)
("M5" 0.0366 0.1516 34.8263 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x8" "A2[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW64x8" "A2[0]" '(0.6)
defineHierAntennaProp "SRAM2RW64x8" "A2[0]" '(
("M1" 0.0366 0.820118 0 0 0.820118 0 0)
("M2" 0.0366 0.1516 22.4061 0 0.1516 0 0)
("M3" 0.0366 0.1516 26.5464 0 0.1516 0 0)
("M4" 0.0366 0.1516 30.6865 0 0.1516 0 0)
("M5" 0.0366 0.1516 34.8263 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x8" "A2[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW64x8" "A2[1]" '(0.6)
defineHierAntennaProp "SRAM2RW64x8" "A2[1]" '(
("M1" 0.0366 0.820118 0 0 0.820118 0 0)
("M2" 0.0366 0.1516 22.4061 0 0.1516 0 0)
("M3" 0.0366 0.1516 26.5464 0 0.1516 0 0)
("M4" 0.0366 0.1516 30.6865 0 0.1516 0 0)
("M5" 0.0366 0.1516 34.8263 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x8" "A2[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW64x8" "A2[2]" '(0.6)
defineHierAntennaProp "SRAM2RW64x8" "A2[2]" '(
("M1" 0.0366 0.820118 0 0 0.820118 0 0)
("M2" 0.0366 0.1516 22.4061 0 0.1516 0 0)
("M3" 0.0366 0.1516 26.5464 0 0.1516 0 0)
("M4" 0.0366 0.1516 30.6865 0 0.1516 0 0)
("M5" 0.0366 0.1516 34.8263 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x8" "A2[3]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW64x8" "A2[3]" '(0.6)
defineHierAntennaProp "SRAM2RW64x8" "A2[3]" '(
("M1" 0.0366 0.820118 0 0 0.820118 0 0)
("M2" 0.0366 0.1516 22.4061 0 0.1516 0 0)
("M3" 0.0366 0.1516 26.5464 0 0.1516 0 0)
("M4" 0.0366 0.1516 30.6865 0 0.1516 0 0)
("M5" 0.0366 0.1516 34.8263 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x8" "I1[5]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x8" "I1[5]" '(0.6)
defineHierAntennaProp "SRAM2RW64x8" "I1[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28566 1.24827 0 1.28566 0 0)
("M4" 0.021 0.1516 62.4661 0 0.1516 0 0)
("M5" 0.021 0.1516 69.6805 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x8" "I1[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x8" "I1[2]" '(0.6)
defineHierAntennaProp "SRAM2RW64x8" "I1[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28566 1.24827 0 1.28566 0 0)
("M4" 0.021 0.1516 62.4661 0 0.1516 0 0)
("M5" 0.021 0.1516 69.6805 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x8" "O1[4]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x8" "O1[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.26188 0 0 0.26188 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x8" "I1[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x8" "I1[3]" '(0.6)
defineHierAntennaProp "SRAM2RW64x8" "I1[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28566 1.24827 0 1.28566 0 0)
("M4" 0.021 0.1516 62.4661 0 0.1516 0 0)
("M5" 0.021 0.1516 69.6805 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x8" "O1[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x8" "O1[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.26188 0 0 0.26188 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x8" "O1[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x8" "O1[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.26188 0 0 0.26188 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x8" "I1[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x8" "I1[1]" '(0.6)
defineHierAntennaProp "SRAM2RW64x8" "I1[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28566 1.24827 0 1.28566 0 0)
("M4" 0.021 0.1516 62.4661 0 0.1516 0 0)
("M5" 0.021 0.1516 69.6805 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x8" "I1[4]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x8" "I1[4]" '(0.6)
defineHierAntennaProp "SRAM2RW64x8" "I1[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28566 1.24827 0 1.28566 0 0)
("M4" 0.021 0.1516 62.4661 0 0.1516 0 0)
("M5" 0.021 0.1516 69.6805 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x8" "I1[6]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x8" "I1[6]" '(0.6)
defineHierAntennaProp "SRAM2RW64x8" "I1[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28566 1.24827 0 1.28566 0 0)
("M4" 0.021 0.1516 62.4661 0 0.1516 0 0)
("M5" 0.021 0.1516 69.6805 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x8" "O1[6]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x8" "O1[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.26188 0 0 0.26188 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x8" "O1[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x8" "O1[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.26188 0 0 0.26188 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x8" "I1[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x8" "I1[0]" '(0.6)
defineHierAntennaProp "SRAM2RW64x8" "I1[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28566 1.24827 0 1.28566 0 0)
("M4" 0.021 0.1516 62.4661 0 0.1516 0 0)
("M5" 0.021 0.1516 69.6805 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x8" "A1[4]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW64x8" "A1[4]" '(0.6)
defineHierAntennaProp "SRAM2RW64x8" "A1[4]" '(
("M1" 0.0366 0.820118 0 0 0.820118 0 0)
("M2" 0.0366 0.1516 22.4061 0 0.1516 0 0)
("M3" 0.0366 0.1516 26.5464 0 0.1516 0 0)
("M4" 0.0366 0.1516 30.6865 0 0.1516 0 0)
("M5" 0.0366 0.1516 34.8263 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x8" "A1[3]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW64x8" "A1[3]" '(0.6)
defineHierAntennaProp "SRAM2RW64x8" "A1[3]" '(
("M1" 0.0366 0.820118 0 0 0.820118 0 0)
("M2" 0.0366 0.1516 22.4061 0 0.1516 0 0)
("M3" 0.0366 0.1516 26.5464 0 0.1516 0 0)
("M4" 0.0366 0.1516 30.6865 0 0.1516 0 0)
("M5" 0.0366 0.1516 34.8263 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x8" "A1[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW64x8" "A1[2]" '(0.6)
defineHierAntennaProp "SRAM2RW64x8" "A1[2]" '(
("M1" 0.0366 0.820118 0 0 0.820118 0 0)
("M2" 0.0366 0.1516 22.4061 0 0.1516 0 0)
("M3" 0.0366 0.1516 26.5464 0 0.1516 0 0)
("M4" 0.0366 0.1516 30.6865 0 0.1516 0 0)
("M5" 0.0366 0.1516 34.8263 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x8" "A1[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW64x8" "A1[1]" '(0.6)
defineHierAntennaProp "SRAM2RW64x8" "A1[1]" '(
("M1" 0.0366 0.820118 0 0 0.820118 0 0)
("M2" 0.0366 0.1516 22.4061 0 0.1516 0 0)
("M3" 0.0366 0.1516 26.5464 0 0.1516 0 0)
("M4" 0.0366 0.1516 30.6865 0 0.1516 0 0)
("M5" 0.0366 0.1516 34.8263 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x8" "A1[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW64x8" "A1[0]" '(0.6)
defineHierAntennaProp "SRAM2RW64x8" "A1[0]" '(
("M1" 0.0366 0.820118 0 0 0.820118 0 0)
("M2" 0.0366 0.1516 22.4061 0 0.1516 0 0)
("M3" 0.0366 0.1516 26.5464 0 0.1516 0 0)
("M4" 0.0366 0.1516 30.6865 0 0.1516 0 0)
("M5" 0.0366 0.1516 34.8263 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x8" "CSB2" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW64x8" "CSB2" '(0.6)
defineHierAntennaProp "SRAM2RW64x8" "CSB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0366 0.40684 1.96052 0 0.40684 0 0)
("M5" 0.0366 0.1516 13.0755 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x8" "A1[5]" '(0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x8" "A1[5]" '(0.6)
defineHierAntennaProp "SRAM2RW64x8" "A1[5]" '(
("M1" 0.021 1.13705 0 0 1.13705 0 0)
("M2" 0.021 0.1516 54.1417 0 0.1516 0 0)
("M3" 0.021 0.1516 61.3567 0 0.1516 0 0)
("M4" 0.021 0.1516 68.5712 0 0.1516 0 0)
("M5" 0.021 0.1516 75.7852 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x8" "CE1" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineDiodeProtection "SRAM2RW64x8" "CE1" '(0.6)
defineHierAntennaProp "SRAM2RW64x8" "CE1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0342 0.29968 3.80244 0 0.29968 0 0)
("M5" 0.0342 0.1516 12.5642 0 0.1516 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x8" "CSB1" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW64x8" "CSB1" '(0.6)
defineHierAntennaProp "SRAM2RW64x8" "CSB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0366 0.424789 1.92429 0 0.424789 0 0)
("M5" 0.0366 0.1516 13.5297 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x8" "VDD" '(0 0 0 0 3.0816 3.0816 3.0816 3.0816 3.0816 3.0816)
defineDiodeProtection "SRAM2RW64x8" "VDD" '(0 0 0 0 117.1787 117.1787 117.1787 117.1787 117.1787 117.1787)
defineHierAntennaProp "SRAM2RW64x8" "VDD" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 3.0816 1727.18 29.0976 0 1727.18 0 0)
("M6" 3.0816 0 0 0 0 0 0)
("M7" 3.0816 0 0 0 0 0 0)
("M8" 3.0816 0 0 0 0 0 0)
("M9" 3.0816 0 0 0 0 0 0)
("MRDL" 3.0816 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "A2[3]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM2RW64x16" "A2[3]" '(
("M1" 0.0366 0.820118 0 0 0.820118 0 0)
("M2" 0.0366 0.1516 22.4061 0 0.1516 0 0)
("M3" 0.0366 0.1516 26.5464 0 0.1516 0 0)
("M4" 0.0366 0.1516 30.6865 0 0.1516 0 0)
("M5" 0.0366 0.1516 34.8263 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "A2[5]" '(0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW64x16" "A2[5]" '(
("M1" 0.021 0.97657 0 0 0.97657 0 0)
("M2" 0.021 0.1516 46.5003 0 0.1516 0 0)
("M3" 0.021 0.1516 53.7158 0 0.1516 0 0)
("M4" 0.021 0.1516 60.9308 0 0.1516 0 0)
("M5" 0.021 0.1516 68.1454 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x16" "O2[4]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x16" "O2[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "VSS" '(0 0 0 0 2.745 2.745 2.745 2.745 2.745 2.745)
defineDiodeProtection "SRAM2RW64x16" "VSS" '(0 0 0 0 18.9924 18.9924 18.9924 18.9924 18.9924 18.9924)
defineHierAntennaProp "SRAM2RW64x16" "VSS" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 2.745 587.72 86.3142 0 587.72 0 0)
("M6" 2.745 0 0 0 0 0 0)
("M7" 2.745 0 0 0 0 0 0)
("M8" 2.745 0 0 0 0 0 0)
("M9" 2.745 0 0 0 0 0 0)
("MRDL" 2.745 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "A1[5]" '(0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW64x16" "A1[5]" '(
("M1" 0.021 1.13705 0 0 1.13705 0 0)
("M2" 0.021 0.1516 54.1417 0 0.1516 0 0)
("M3" 0.021 0.1516 61.3567 0 0.1516 0 0)
("M4" 0.021 0.1516 68.5712 0 0.1516 0 0)
("M5" 0.021 0.1516 75.7852 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "CE1" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineHierAntennaProp "SRAM2RW64x16" "CE1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0342 0.29968 3.80244 0 0.29968 0 0)
("M5" 0.0342 0.1516 12.5642 0 0.1516 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "CSB1" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM2RW64x16" "CSB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0366 0.424789 1.92429 0 0.424789 0 0)
("M5" 0.0366 0.1516 13.5297 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "VDD" '(0 0 0 0 3.0816 3.0816 3.0816 3.0816 3.0816 3.0816)
defineDiodeProtection "SRAM2RW64x16" "VDD" '(0 0 0 0 173.4348 173.4348 173.4348 173.4348 173.4348 173.4348)
defineHierAntennaProp "SRAM2RW64x16" "VDD" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 3.0816 2451.91 29.4589 0 2451.91 0 0)
("M6" 3.0816 0 0 0 0 0 0)
("M7" 3.0816 0 0 0 0 0 0)
("M8" 3.0816 0 0 0 0 0 0)
("M9" 3.0816 0 0 0 0 0 0)
("MRDL" 3.0816 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x16" "O1[13]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x16" "O1[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x16" "O1[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x16" "O1[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "I1[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW64x16" "I1[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x16" "O1[10]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x16" "O1[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "I1[10]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW64x16" "I1[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x16" "O1[8]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x16" "O1[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "I1[8]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x16" "I1[8]" '(0.6)
defineHierAntennaProp "SRAM2RW64x16" "I1[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "OEB1" '(0 0.2682 0.2682 0.2682 0.2682 0.2682 0.2682 0.2682 0.2682 0.2682)
defineDiodeProtection "SRAM2RW64x16" "OEB1" '(0.6)
defineHierAntennaProp "SRAM2RW64x16" "OEB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.2682 1.56982 0.96602 0 1.56982 0 0)
("M3" 0.2682 0.1516 6.81874 0 0.1516 0 0)
("M4" 0.2682 0.1516 7.3835 0 0.1516 0 0)
("M5" 0.2682 0.1516 7.94823 0 0.1516 0 0)
("M6" 0.2682 0 0 0 0 0 0)
("M7" 0.2682 0 0 0 0 0 0)
("M8" 0.2682 0 0 0 0 0 0)
("M9" 0.2682 0 0 0 0 0 0)
("MRDL" 0.2682 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "OEB2" '(0 0.2682 0.2682 0.2682 0.2682 0.2682 0.2682 0.2682 0.2682 0.2682)
defineDiodeProtection "SRAM2RW64x16" "OEB2" '(0.6)
defineHierAntennaProp "SRAM2RW64x16" "OEB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.2682 1.564 0.96602 0 1.564 0 0)
("M3" 0.2682 0.1516 6.79704 0 0.1516 0 0)
("M4" 0.2682 0.1516 7.3618 0 0.1516 0 0)
("M5" 0.2682 0.1516 7.92653 0 0.1516 0 0)
("M6" 0.2682 0 0 0 0 0 0)
("M7" 0.2682 0 0 0 0 0 0)
("M8" 0.2682 0 0 0 0 0 0)
("M9" 0.2682 0 0 0 0 0 0)
("MRDL" 0.2682 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "WEB2" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineDiodeProtection "SRAM2RW64x16" "WEB2" '(0.6)
defineHierAntennaProp "SRAM2RW64x16" "WEB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1461 1.56742 1.03833 0 1.56742 0 0)
("M3" 0.1461 0.1516 11.766 0 0.1516 0 0)
("M4" 0.1461 0.1516 12.8028 0 0.1516 0 0)
("M5" 0.1461 0.1516 13.8395 0 0.1516 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "WEB1" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineDiodeProtection "SRAM2RW64x16" "WEB1" '(0.6)
defineHierAntennaProp "SRAM2RW64x16" "WEB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1461 1.56742 1.03833 0 1.56742 0 0)
("M3" 0.1461 0.1516 11.766 0 0.1516 0 0)
("M4" 0.1461 0.1516 12.8028 0 0.1516 0 0)
("M5" 0.1461 0.1516 13.8395 0 0.1516 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x16" "O1[12]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x16" "O1[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "I1[12]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x16" "I1[12]" '(0.6)
defineHierAntennaProp "SRAM2RW64x16" "I1[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x16" "O1[11]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x16" "O1[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "I1[11]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x16" "I1[11]" '(0.6)
defineHierAntennaProp "SRAM2RW64x16" "I1[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x16" "O1[4]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x16" "O1[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "I1[4]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x16" "I1[4]" '(0.6)
defineHierAntennaProp "SRAM2RW64x16" "I1[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "I1[13]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x16" "I1[13]" '(0.6)
defineHierAntennaProp "SRAM2RW64x16" "I1[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x16" "O1[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x16" "O1[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "I1[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x16" "I1[1]" '(0.6)
defineHierAntennaProp "SRAM2RW64x16" "I1[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x16" "O1[5]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x16" "O1[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "I1[5]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x16" "I1[5]" '(0.6)
defineHierAntennaProp "SRAM2RW64x16" "I1[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x16" "O1[7]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x16" "O1[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x16" "O1[9]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x16" "O1[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "I1[9]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x16" "I1[9]" '(0.6)
defineHierAntennaProp "SRAM2RW64x16" "I1[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x16" "O1[14]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x16" "O1[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "I1[14]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x16" "I1[14]" '(0.6)
defineHierAntennaProp "SRAM2RW64x16" "I1[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x16" "O1[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x16" "O1[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "I1[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x16" "I1[0]" '(0.6)
defineHierAntennaProp "SRAM2RW64x16" "I1[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "I2[13]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x16" "I2[13]" '(0.6)
defineHierAntennaProp "SRAM2RW64x16" "I2[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x16" "O2[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x16" "O2[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "I2[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x16" "I2[1]" '(0.6)
defineHierAntennaProp "SRAM2RW64x16" "I2[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "I2[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x16" "I2[3]" '(0.6)
defineHierAntennaProp "SRAM2RW64x16" "I2[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x16" "O2[10]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x16" "O2[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "I2[10]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x16" "I2[10]" '(0.6)
defineHierAntennaProp "SRAM2RW64x16" "I2[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x16" "O2[8]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x16" "O2[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "I2[8]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x16" "I2[8]" '(0.6)
defineHierAntennaProp "SRAM2RW64x16" "I2[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x16" "O2[9]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x16" "O2[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "I2[9]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x16" "I2[9]" '(0.6)
defineHierAntennaProp "SRAM2RW64x16" "I2[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x16" "O2[14]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x16" "O2[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x16" "O1[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x16" "O1[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "I1[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x16" "I1[2]" '(0.6)
defineHierAntennaProp "SRAM2RW64x16" "I1[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x16" "O1[15]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x16" "O1[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "I1[15]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x16" "I1[15]" '(0.6)
defineHierAntennaProp "SRAM2RW64x16" "I1[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x16" "O1[6]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x16" "O1[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "I1[6]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x16" "I1[6]" '(0.6)
defineHierAntennaProp "SRAM2RW64x16" "I1[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x16" "O2[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x16" "O2[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "I1[7]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x16" "I1[7]" '(0.6)
defineHierAntennaProp "SRAM2RW64x16" "I1[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "I2[4]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x16" "I2[4]" '(0.6)
defineHierAntennaProp "SRAM2RW64x16" "I2[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x16" "O2[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x16" "O2[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "I2[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x16" "I2[2]" '(0.6)
defineHierAntennaProp "SRAM2RW64x16" "I2[2]" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x16" "O2[15]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x16" "O2[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "I2[15]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x16" "I2[15]" '(0.6)
defineHierAntennaProp "SRAM2RW64x16" "I2[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1514 62.3746 0 0.1514 0 0)
("M5" 0.021 0.1514 69.5795 0 0.1514 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x16" "O2[6]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x16" "O2[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "I2[6]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x16" "I2[6]" '(0.6)
defineHierAntennaProp "SRAM2RW64x16" "I2[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x16" "O2[5]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x16" "O2[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "I2[5]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x16" "I2[5]" '(0.6)
defineHierAntennaProp "SRAM2RW64x16" "I2[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x16" "O2[7]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x16" "O2[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "I2[7]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x16" "I2[7]" '(0.6)
defineHierAntennaProp "SRAM2RW64x16" "I2[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x16" "O2[12]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x16" "O2[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "I2[12]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x16" "I2[12]" '(0.6)
defineHierAntennaProp "SRAM2RW64x16" "I2[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x16" "O2[11]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x16" "O2[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "I2[11]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x16" "I2[11]" '(0.6)
defineHierAntennaProp "SRAM2RW64x16" "I2[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "I2[14]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x16" "I2[14]" '(0.6)
defineHierAntennaProp "SRAM2RW64x16" "I2[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x16" "O2[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x16" "O2[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "I2[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x16" "I2[0]" '(0.6)
defineHierAntennaProp "SRAM2RW64x16" "I2[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x16" "O2[13]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x16" "O2[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "A1[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW64x16" "A1[0]" '(0.6)
defineHierAntennaProp "SRAM2RW64x16" "A1[0]" '(
("M1" 0.0366 0.820118 0 0 0.820118 0 0)
("M2" 0.0366 0.1516 22.4061 0 0.1516 0 0)
("M3" 0.0366 0.1516 26.5464 0 0.1516 0 0)
("M4" 0.0366 0.1516 30.6865 0 0.1516 0 0)
("M5" 0.0366 0.1516 34.8263 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "A1[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW64x16" "A1[2]" '(0.6)
defineHierAntennaProp "SRAM2RW64x16" "A1[2]" '(
("M1" 0.0366 0.820118 0 0 0.820118 0 0)
("M2" 0.0366 0.1516 22.4061 0 0.1516 0 0)
("M3" 0.0366 0.1516 26.5464 0 0.1516 0 0)
("M4" 0.0366 0.1516 30.6865 0 0.1516 0 0)
("M5" 0.0366 0.1516 34.8263 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "A1[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW64x16" "A1[1]" '(0.6)
defineHierAntennaProp "SRAM2RW64x16" "A1[1]" '(
("M1" 0.0366 0.820118 0 0 0.820118 0 0)
("M2" 0.0366 0.1516 22.4061 0 0.1516 0 0)
("M3" 0.0366 0.1516 26.5464 0 0.1516 0 0)
("M4" 0.0366 0.1516 30.6865 0 0.1516 0 0)
("M5" 0.0366 0.1516 34.8263 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "A1[3]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW64x16" "A1[3]" '(0.6)
defineHierAntennaProp "SRAM2RW64x16" "A1[3]" '(
("M1" 0.0366 0.820118 0 0 0.820118 0 0)
("M2" 0.0366 0.1516 22.4061 0 0.1516 0 0)
("M3" 0.0366 0.1516 26.5464 0 0.1516 0 0)
("M4" 0.0366 0.1516 30.6865 0 0.1516 0 0)
("M5" 0.0366 0.1516 34.8263 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "A1[4]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW64x16" "A1[4]" '(0.6)
defineHierAntennaProp "SRAM2RW64x16" "A1[4]" '(
("M1" 0.0366 0.820118 0 0 0.820118 0 0)
("M2" 0.0366 0.1516 22.4061 0 0.1516 0 0)
("M3" 0.0366 0.1516 26.5464 0 0.1516 0 0)
("M4" 0.0366 0.1516 30.6865 0 0.1516 0 0)
("M5" 0.0366 0.1516 34.8263 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "CE2" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineDiodeProtection "SRAM2RW64x16" "CE2" '(0.6)
defineHierAntennaProp "SRAM2RW64x16" "CE2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0342 0.30916 3.47688 0 0.30916 0 0)
("M5" 0.0342 0.1516 12.5158 0 0.1516 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "CSB2" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW64x16" "CSB2" '(0.6)
defineHierAntennaProp "SRAM2RW64x16" "CSB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0366 0.40684 1.96052 0 0.40684 0 0)
("M5" 0.0366 0.1516 13.0755 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "A2[0]" '(0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW64x16" "A2[0]" '(0.6)
defineHierAntennaProp "SRAM2RW64x16" "A2[0]" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0.0366 0.1516 21.5865 0 0.1516 0 0)
("M3" 0.0366 0.1516 25.7269 0 0.1516 0 0)
("M4" 0.0366 0.1516 29.867 0 0.1516 0 0)
("M5" 0.0366 0.1516 34.0068 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "A2[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW64x16" "A2[2]" '(0.6)
defineHierAntennaProp "SRAM2RW64x16" "A2[2]" '(
("M1" 0.0366 0.820118 0 0 0.820118 0 0)
("M2" 0.0366 0.1516 22.4061 0 0.1516 0 0)
("M3" 0.0366 0.1516 26.5464 0 0.1516 0 0)
("M4" 0.0366 0.1516 30.6865 0 0.1516 0 0)
("M5" 0.0366 0.1516 34.8263 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "A2[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW64x16" "A2[1]" '(0.6)
defineHierAntennaProp "SRAM2RW64x16" "A2[1]" '(
("M1" 0.0366 0.820118 0 0 0.820118 0 0)
("M2" 0.0366 0.1516 22.4061 0 0.1516 0 0)
("M3" 0.0366 0.1516 26.5464 0 0.1516 0 0)
("M4" 0.0366 0.1516 30.6865 0 0.1516 0 0)
("M5" 0.0366 0.1516 34.8263 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x16" "A2[4]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW64x16" "A2[4]" '(0.6)
defineHierAntennaProp "SRAM2RW64x16" "A2[4]" '(
("M1" 0.0366 0.820118 0 0 0.820118 0 0)
("M2" 0.0366 0.1516 22.4061 0 0.1516 0 0)
("M3" 0.0366 0.1516 26.5464 0 0.1516 0 0)
("M4" 0.0366 0.1516 30.6865 0 0.1516 0 0)
("M5" 0.0366 0.1516 34.8263 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I1[25]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW64x32" "I1[25]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I1[31]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW64x32" "I1[31]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I1[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW64x32" "I1[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I1[23]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW64x32" "I1[23]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O1[31]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O1[31]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O1[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O1[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O1[23]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O1[23]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I1[26]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW64x32" "I1[26]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.29343 1.24826 0 1.29343 0 0)
("M4" 0.021 0.1516 62.836 0 0.1516 0 0)
("M5" 0.021 0.1516 70.0504 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O1[25]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O1[25]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O1[29]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O1[29]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O1[22]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O1[22]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O1[26]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O1[26]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I1[29]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I1[29]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I1[29]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I1[22]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I1[22]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I1[22]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O1[15]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O1[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O1[21]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O1[21]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O1[6]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O1[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O1[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O1[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I1[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I1[2]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I1[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I1[6]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I1[6]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I1[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O1[14]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O1[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O1[30]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O1[30]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O1[19]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O1[19]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I1[5]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I1[5]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I1[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I1[30]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I1[30]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I1[30]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I1[19]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I1[19]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I1[19]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O1[13]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O1[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I1[13]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I1[13]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I1[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O1[5]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O1[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O1[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O1[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I1[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I1[1]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I1[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O1[4]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O1[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O1[11]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O1[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O1[28]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O1[28]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I2[18]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I2[18]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I2[18]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I2[7]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I2[7]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I2[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O2[18]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O2[18]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O2[7]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O2[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O2[24]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O2[24]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I2[17]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I2[17]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I2[17]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O2[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O2[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O2[9]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O2[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O2[10]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O2[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I2[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I2[3]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I2[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I2[9]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I2[9]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I2[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I2[10]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I2[10]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I2[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O2[17]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O2[17]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O2[16]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O2[16]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I2[16]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I2[16]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I2[16]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O2[12]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O2[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O2[8]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O2[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I2[12]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I2[12]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I2[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I2[8]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I2[8]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I2[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "A1[4]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW64x32" "A1[4]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "A1[4]" '(
("M1" 0.0366 0.820118 0 0 0.820118 0 0)
("M2" 0.0366 0.1516 22.4061 0 0.1516 0 0)
("M3" 0.0366 0.1516 26.5464 0 0.1516 0 0)
("M4" 0.0366 0.1516 30.6865 0 0.1516 0 0)
("M5" 0.0366 0.1516 34.8263 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "A1[3]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW64x32" "A1[3]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "A1[3]" '(
("M1" 0.0366 0.820118 0 0 0.820118 0 0)
("M2" 0.0366 0.1516 22.4061 0 0.1516 0 0)
("M3" 0.0366 0.1516 26.5464 0 0.1516 0 0)
("M4" 0.0366 0.1516 30.6865 0 0.1516 0 0)
("M5" 0.0366 0.1516 34.8263 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "A1[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW64x32" "A1[2]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "A1[2]" '(
("M1" 0.0366 0.820118 0 0 0.820118 0 0)
("M2" 0.0366 0.1516 22.4061 0 0.1516 0 0)
("M3" 0.0366 0.1516 26.5464 0 0.1516 0 0)
("M4" 0.0366 0.1516 30.6865 0 0.1516 0 0)
("M5" 0.0366 0.1516 34.8263 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "A1[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW64x32" "A1[1]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "A1[1]" '(
("M1" 0.0366 0.820118 0 0 0.820118 0 0)
("M2" 0.0366 0.1516 22.4061 0 0.1516 0 0)
("M3" 0.0366 0.1516 26.5464 0 0.1516 0 0)
("M4" 0.0366 0.1516 30.6865 0 0.1516 0 0)
("M5" 0.0366 0.1516 34.8263 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "A1[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW64x32" "A1[0]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "A1[0]" '(
("M1" 0.0366 0.820118 0 0 0.820118 0 0)
("M2" 0.0366 0.1516 22.4061 0 0.1516 0 0)
("M3" 0.0366 0.1516 26.5464 0 0.1516 0 0)
("M4" 0.0366 0.1516 30.6865 0 0.1516 0 0)
("M5" 0.0366 0.1516 34.8263 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "CSB2" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW64x32" "CSB2" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "CSB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0366 0.40684 1.96052 0 0.40684 0 0)
("M5" 0.0366 0.1516 13.0755 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "CE2" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineDiodeProtection "SRAM2RW64x32" "CE2" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "CE2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0342 0.30916 3.47688 0 0.30916 0 0)
("M5" 0.0342 0.1516 12.5158 0 0.1516 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "A2[5]" '(0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "A2[5]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "A2[5]" '(
("M1" 0.021 0.97657 0 0 0.97657 0 0)
("M2" 0.021 0.1516 46.5003 0 0.1516 0 0)
("M3" 0.021 0.1516 53.7158 0 0.1516 0 0)
("M4" 0.021 0.1516 60.9308 0 0.1516 0 0)
("M5" 0.021 0.1516 68.1454 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "A2[4]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW64x32" "A2[4]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "A2[4]" '(
("M1" 0.0366 0.820118 0 0 0.820118 0 0)
("M2" 0.0366 0.1516 22.4061 0 0.1516 0 0)
("M3" 0.0366 0.1516 26.5464 0 0.1516 0 0)
("M4" 0.0366 0.1516 30.6865 0 0.1516 0 0)
("M5" 0.0366 0.1516 34.8263 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "A2[3]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW64x32" "A2[3]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "A2[3]" '(
("M1" 0.0366 0.820118 0 0 0.820118 0 0)
("M2" 0.0366 0.1516 22.4061 0 0.1516 0 0)
("M3" 0.0366 0.1516 26.5464 0 0.1516 0 0)
("M4" 0.0366 0.1516 30.6865 0 0.1516 0 0)
("M5" 0.0366 0.1516 34.8263 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "A2[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW64x32" "A2[2]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "A2[2]" '(
("M1" 0.0366 0.820118 0 0 0.820118 0 0)
("M2" 0.0366 0.1516 22.4061 0 0.1516 0 0)
("M3" 0.0366 0.1516 26.5464 0 0.1516 0 0)
("M4" 0.0366 0.1516 30.6865 0 0.1516 0 0)
("M5" 0.0366 0.1516 34.8263 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "A2[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW64x32" "A2[0]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "A2[0]" '(
("M1" 0.0366 0.820118 0 0 0.820118 0 0)
("M2" 0.0366 0.1516 22.4061 0 0.1516 0 0)
("M3" 0.0366 0.1516 26.5464 0 0.1516 0 0)
("M4" 0.0366 0.1516 30.6865 0 0.1516 0 0)
("M5" 0.0366 0.1516 34.8263 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "A2[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW64x32" "A2[1]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "A2[1]" '(
("M1" 0.0366 0.820118 0 0 0.820118 0 0)
("M2" 0.0366 0.1516 22.4061 0 0.1516 0 0)
("M3" 0.0366 0.1516 26.5464 0 0.1516 0 0)
("M4" 0.0366 0.1516 30.6865 0 0.1516 0 0)
("M5" 0.0366 0.1516 34.8263 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I2[20]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I2[20]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I2[20]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "VSS" '(0 0 0 0 5.49 5.49 5.49 5.49 5.49 5.49)
defineDiodeProtection "SRAM2RW64x32" "VSS" '(0 0 0 0 296.6099 296.6099 296.6099 296.6099 296.6099 296.6099)
defineHierAntennaProp "SRAM2RW64x32" "VSS" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 5.49 4054.16 86.3142 0 4054.16 0 0)
("M6" 5.49 0 0 0 0 0 0)
("M7" 5.49 0 0 0 0 0 0)
("M8" 5.49 0 0 0 0 0 0)
("M9" 5.49 0 0 0 0 0 0)
("MRDL" 5.49 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "CE1" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineDiodeProtection "SRAM2RW64x32" "CE1" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "CE1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0342 0.29968 3.80244 0 0.29968 0 0)
("M5" 0.0342 0.1516 12.5642 0 0.1516 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "A1[5]" '(0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "A1[5]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "A1[5]" '(
("M1" 0.021 1.13705 0 0 1.13705 0 0)
("M2" 0.021 0.1516 54.1417 0 0.1516 0 0)
("M3" 0.021 0.1516 61.3567 0 0.1516 0 0)
("M4" 0.021 0.1516 68.5712 0 0.1516 0 0)
("M5" 0.021 0.1516 75.7852 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "CSB1" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW64x32" "CSB1" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "CSB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0366 0.424789 1.92429 0 0.424789 0 0)
("M5" 0.0366 0.1516 13.5297 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "VDD" '(0 0 0 0 3.0816 3.0816 3.0816 3.0816 3.0816 3.0816)
defineDiodeProtection "SRAM2RW64x32" "VDD" '(0 0 0 0 285.9469 285.9469 285.9469 285.9469 285.9469 285.9469)
defineHierAntennaProp "SRAM2RW64x32" "VDD" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 3.0816 4054.16 29.5894 0 4054.16 0 0)
("M6" 3.0816 0 0 0 0 0 0)
("M7" 3.0816 0 0 0 0 0 0)
("M8" 3.0816 0 0 0 0 0 0)
("M9" 3.0816 0 0 0 0 0 0)
("MRDL" 3.0816 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O1[16]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O1[16]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "WEB2" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineDiodeProtection "SRAM2RW64x32" "WEB2" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "WEB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1461 1.56742 1.03833 0 1.56742 0 0)
("M3" 0.1461 0.1516 11.766 0 0.1516 0 0)
("M4" 0.1461 0.1516 12.8028 0 0.1516 0 0)
("M5" 0.1461 0.1516 13.8395 0 0.1516 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I2[23]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I2[23]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I2[23]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O2[26]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O2[26]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I2[21]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I2[21]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I2[21]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I2[22]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I2[22]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I2[22]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I2[29]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I2[29]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I2[29]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O2[21]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O2[21]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O2[29]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O2[29]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O2[22]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O2[22]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O2[15]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O2[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I2[27]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I2[27]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I2[27]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I2[15]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I2[15]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I2[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O2[20]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O2[20]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O2[27]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O2[27]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I2[24]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I2[24]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I2[24]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I1[15]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I1[15]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I1[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I2[13]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I2[13]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I2[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I1[4]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I1[4]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I1[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "WEB1" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineDiodeProtection "SRAM2RW64x32" "WEB1" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "WEB1" '(
("M1" 0 0.15352 0 0 0.15352 0 0)
("M2" 0.1461 1.56742 1.03833 0 1.56742 0 0)
("M3" 0.1461 0.15352 11.766 0 0.15352 0 0)
("M4" 0.1461 0.15352 12.8159 0 0.15352 0 0)
("M5" 0.1461 0.15352 13.8658 0 0.15352 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I2[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I2[1]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I2[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "OEB1" '(0 0.5178 0.5178 0.5178 0.5178 0.5178 0.5178 0.5178 0.5178 0.5178)
defineDiodeProtection "SRAM2RW64x32" "OEB1" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "OEB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.5178 2.8876 0.966022 0 2.8876 0 0)
("M3" 0.5178 0.1516 6.54226 0 0.1516 0 0)
("M4" 0.5178 0.1516 6.83459 0 0.1516 0 0)
("M5" 0.5178 0.1516 7.12689 0 0.1516 0 0)
("M6" 0.5178 0 0 0 0 0 0)
("M7" 0.5178 0 0 0 0 0 0)
("M8" 0.5178 0 0 0 0 0 0)
("M9" 0.5178 0 0 0 0 0 0)
("MRDL" 0.5178 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I2[5]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I2[5]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I2[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I2[30]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I2[30]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I2[30]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O2[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O2[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O2[4]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O2[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O2[11]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O2[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O2[28]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O2[28]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I2[25]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I2[25]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I2[25]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I2[4]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I2[4]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I2[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I2[11]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I2[11]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I2[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I2[28]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I2[28]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I2[28]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O2[31]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O2[31]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O2[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O2[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O2[23]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O2[23]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O2[25]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O2[25]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I2[26]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I2[26]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I2[26]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I2[31]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I2[31]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I2[31]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I2[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I2[0]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I2[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I1[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I1[3]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I1[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O1[12]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O1[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O1[8]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O1[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O2[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O2[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I1[8]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I1[8]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I1[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I1[16]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I1[16]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I1[16]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I1[12]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I1[12]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I1[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O1[10]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O1[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O2[19]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O2[19]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O2[14]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O2[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O2[6]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O2[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I2[19]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I2[19]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I2[19]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I2[14]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I2[14]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I2[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I2[6]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I2[6]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I2[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I2[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I2[2]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I2[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O2[13]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O2[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O2[5]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O2[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O2[30]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O2[30]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I1[27]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I1[27]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I1[27]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "OEB2" '(0 0.5178 0.5178 0.5178 0.5178 0.5178 0.5178 0.5178 0.5178 0.5178)
defineDiodeProtection "SRAM2RW64x32" "OEB2" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "OEB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.5178 2.88178 0.966022 0 2.88178 0 0)
("M3" 0.5178 0.1516 6.53102 0 0.1516 0 0)
("M4" 0.5178 0.1516 6.82335 0 0.1516 0 0)
("M5" 0.5178 0.1516 7.11566 0 0.1516 0 0)
("M6" 0.5178 0 0 0 0 0 0)
("M7" 0.5178 0 0 0 0 0 0)
("M8" 0.5178 0 0 0 0 0 0)
("M9" 0.5178 0 0 0 0 0 0)
("MRDL" 0.5178 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I1[21]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I1[21]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I1[21]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I1[20]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I1[20]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I1[20]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O1[24]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O1[24]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O1[20]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O1[20]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I1[24]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I1[24]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I1[24]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O1[27]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O1[27]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O1[18]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O1[18]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O1[7]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O1[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I1[17]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I1[17]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I1[17]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I1[18]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I1[18]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I1[18]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I1[7]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I1[7]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I1[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I1[10]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I1[10]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I1[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I1[9]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I1[9]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I1[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O1[17]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O1[17]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O1[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O1[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW64x32" "O1[9]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW64x32" "O1[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I1[14]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I1[14]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I1[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I1[11]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I1[11]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I1[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW64x32" "I1[28]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW64x32" "I1[28]" '(0.6)
defineHierAntennaProp "SRAM2RW64x32" "I1[28]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x4" "A1[6]" '(0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW128x4" "A1[6]" '(
("M1" 0.021 0.97597 0 0 0.97597 0 0)
("M2" 0.021 0.1516 46.4717 0 0.1516 0 0)
("M3" 0.021 0.1516 53.6872 0 0.1516 0 0)
("M4" 0.021 0.1516 60.9022 0 0.1516 0 0)
("M5" 0.021 0.1516 68.1168 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x4" "A2[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM2RW128x4" "A2[0]" '(
("M1" 0.0366 0.762118 0 0 0.762118 0 0)
("M2" 0.0366 0.1516 20.8215 0 0.1516 0 0)
("M3" 0.0366 0.1516 24.962 0 0.1516 0 0)
("M4" 0.0366 0.1516 29.1021 0 0.1516 0 0)
("M5" 0.0366 0.1516 33.242 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x4" "A2[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM2RW128x4" "A2[1]" '(
("M1" 0.0366 0.762118 0 0 0.762118 0 0)
("M2" 0.0366 0.1516 20.8215 0 0.1516 0 0)
("M3" 0.0366 0.1516 24.962 0 0.1516 0 0)
("M4" 0.0366 0.1516 29.1021 0 0.1516 0 0)
("M5" 0.0366 0.1516 33.242 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x4" "A2[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM2RW128x4" "A2[2]" '(
("M1" 0.0366 0.762118 0 0 0.762118 0 0)
("M2" 0.0366 0.1516 20.8215 0 0.1516 0 0)
("M3" 0.0366 0.1516 24.962 0 0.1516 0 0)
("M4" 0.0366 0.1516 29.1021 0 0.1516 0 0)
("M5" 0.0366 0.1516 33.242 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x4" "A2[3]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM2RW128x4" "A2[3]" '(
("M1" 0.0366 0.762118 0 0 0.762118 0 0)
("M2" 0.0366 0.1516 20.8215 0 0.1516 0 0)
("M3" 0.0366 0.1516 24.962 0 0.1516 0 0)
("M4" 0.0366 0.1516 29.1021 0 0.1516 0 0)
("M5" 0.0366 0.1516 33.242 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x4" "A2[4]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM2RW128x4" "A2[4]" '(
("M1" 0.0366 0.762118 0 0 0.762118 0 0)
("M2" 0.0366 0.1516 20.8215 0 0.1516 0 0)
("M3" 0.0366 0.1516 24.962 0 0.1516 0 0)
("M4" 0.0366 0.1516 29.1021 0 0.1516 0 0)
("M5" 0.0366 0.1516 33.242 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x4" "A2[5]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM2RW128x4" "A2[5]" '(
("M1" 0.0366 0.762118 0 0 0.762118 0 0)
("M2" 0.0366 0.1516 20.8215 0 0.1516 0 0)
("M3" 0.0366 0.1516 24.962 0 0.1516 0 0)
("M4" 0.0366 0.1516 29.1021 0 0.1516 0 0)
("M5" 0.0366 0.1516 33.242 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x4" "A2[6]" '(0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW128x4" "A2[6]" '(
("M1" 0.021 0.96757 0 0 0.96757 0 0)
("M2" 0.021 0.1516 46.0717 0 0.1516 0 0)
("M3" 0.021 0.1516 53.2873 0 0.1516 0 0)
("M4" 0.021 0.1516 60.5023 0 0.1516 0 0)
("M5" 0.021 0.1516 67.7169 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x4" "CE2" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineHierAntennaProp "SRAM2RW128x4" "CE2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0342 0.28402 3.98538 0 0.28402 0 0)
("M5" 0.0342 0.1516 12.2892 0 0.1516 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x4" "CSB2" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM2RW128x4" "CSB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0366 0.412296 2.20408 0 0.412296 0 0)
("M5" 0.0366 0.1516 13.4681 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x4" "A1[3]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM2RW128x4" "A1[3]" '(
("M1" 0.0366 0.770518 0 0 0.770518 0 0)
("M2" 0.0366 0.1516 21.051 0 0.1516 0 0)
("M3" 0.0366 0.1516 25.1914 0 0.1516 0 0)
("M4" 0.0366 0.1516 29.3316 0 0.1516 0 0)
("M5" 0.0366 0.1516 33.4714 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x4" "A1[4]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM2RW128x4" "A1[4]" '(
("M1" 0.0366 0.770518 0 0 0.770518 0 0)
("M2" 0.0366 0.1516 21.051 0 0.1516 0 0)
("M3" 0.0366 0.1516 25.1914 0 0.1516 0 0)
("M4" 0.0366 0.1516 29.3316 0 0.1516 0 0)
("M5" 0.0366 0.1516 33.4714 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x4" "A1[5]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW128x4" "A1[5]" '(0.6)
defineHierAntennaProp "SRAM2RW128x4" "A1[5]" '(
("M1" 0.0366 0.770518 0 0 0.770518 0 0)
("M2" 0.0366 0.1516 21.051 0 0.1516 0 0)
("M3" 0.0366 0.1516 25.1914 0 0.1516 0 0)
("M4" 0.0366 0.1516 29.3316 0 0.1516 0 0)
("M5" 0.0366 0.1516 33.4714 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x4" "O1[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x4" "O1[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x4" "O1[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x4" "O1[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x4" "I2[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x4" "I2[3]" '(0.6)
defineHierAntennaProp "SRAM2RW128x4" "I2[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x4" "OEB2" '(0 0.081 0.081 0.081 0.081 0.081 0.081 0.081 0.081 0.081)
defineDiodeProtection "SRAM2RW128x4" "OEB2" '(0.6)
defineHierAntennaProp "SRAM2RW128x4" "OEB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.081 0.59387 0.966009 0 0.59387 0 0)
("M3" 0.081 0.1516 8.2972 0 0.1516 0 0)
("M4" 0.081 0.1516 10.1681 0 0.1516 0 0)
("M5" 0.081 0.1516 12.0389 0 0.1516 0 0)
("M6" 0.081 0 0 0 0 0 0)
("M7" 0.081 0 0 0 0 0 0)
("M8" 0.081 0 0 0 0 0 0)
("M9" 0.081 0 0 0 0 0 0)
("MRDL" 0.081 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x4" "WEB1" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineDiodeProtection "SRAM2RW128x4" "WEB1" '(0.6)
defineHierAntennaProp "SRAM2RW128x4" "WEB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1461 1.5667 1.03833 0 1.5667 0 0)
("M3" 0.1461 0.1516 11.761 0 0.1516 0 0)
("M4" 0.1461 0.1516 12.7978 0 0.1516 0 0)
("M5" 0.1461 0.1516 13.8346 0 0.1516 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x4" "A1[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW128x4" "A1[1]" '(0.6)
defineHierAntennaProp "SRAM2RW128x4" "A1[1]" '(
("M1" 0.0366 0.770518 0 0 0.770518 0 0)
("M2" 0.0366 0.1516 21.051 0 0.1516 0 0)
("M3" 0.0366 0.1516 25.1914 0 0.1516 0 0)
("M4" 0.0366 0.1516 29.3316 0 0.1516 0 0)
("M5" 0.0366 0.1516 33.4714 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x4" "O2[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x4" "O2[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.265273 0 0 0.265273 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x4" "OEB1" '(0 0.081 0.081 0.081 0.081 0.081 0.081 0.081 0.081 0.081)
defineDiodeProtection "SRAM2RW128x4" "OEB1" '(0.6)
defineHierAntennaProp "SRAM2RW128x4" "OEB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.081 0.60492 0.96601 0 0.60492 0 0)
("M3" 0.081 0.1516 8.43361 0 0.1516 0 0)
("M4" 0.081 0.1516 10.3045 0 0.1516 0 0)
("M5" 0.081 0.1516 12.1753 0 0.1516 0 0)
("M6" 0.081 0 0 0 0 0 0)
("M7" 0.081 0 0 0 0 0 0)
("M8" 0.081 0 0 0 0 0 0)
("M9" 0.081 0 0 0 0 0 0)
("MRDL" 0.081 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x4" "I2[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x4" "I2[2]" '(0.6)
defineHierAntennaProp "SRAM2RW128x4" "I2[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x4" "O2[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x4" "O2[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x4" "I2[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x4" "I2[0]" '(0.6)
defineHierAntennaProp "SRAM2RW128x4" "I2[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x4" "I2[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x4" "I2[1]" '(0.6)
defineHierAntennaProp "SRAM2RW128x4" "I2[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x4" "O2[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x4" "O2[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x4" "I1[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x4" "I1[3]" '(0.6)
defineHierAntennaProp "SRAM2RW128x4" "I1[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x4" "O1[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x4" "O1[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x4" "I1[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x4" "I1[2]" '(0.6)
defineHierAntennaProp "SRAM2RW128x4" "I1[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x4" "O2[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x4" "O2[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x4" "O1[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x4" "O1[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x4" "I1[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x4" "I1[0]" '(0.6)
defineHierAntennaProp "SRAM2RW128x4" "I1[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x4" "I1[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x4" "I1[1]" '(0.6)
defineHierAntennaProp "SRAM2RW128x4" "I1[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x4" "CSB1" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW128x4" "CSB1" '(0.6)
defineHierAntennaProp "SRAM2RW128x4" "CSB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0366 0.405635 1.88075 0 0.405635 0 0)
("M5" 0.0366 0.1516 12.9628 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x4" "A1[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW128x4" "A1[2]" '(0.6)
defineHierAntennaProp "SRAM2RW128x4" "A1[2]" '(
("M1" 0.0366 0.770518 0 0 0.770518 0 0)
("M2" 0.0366 0.1516 21.051 0 0.1516 0 0)
("M3" 0.0366 0.1516 25.1914 0 0.1516 0 0)
("M4" 0.0366 0.1516 29.3316 0 0.1516 0 0)
("M5" 0.0366 0.1516 33.4714 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x4" "A1[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW128x4" "A1[0]" '(0.6)
defineHierAntennaProp "SRAM2RW128x4" "A1[0]" '(
("M1" 0.0366 0.770518 0 0 0.770518 0 0)
("M2" 0.0366 0.1516 21.051 0 0.1516 0 0)
("M3" 0.0366 0.1516 25.1914 0 0.1516 0 0)
("M4" 0.0366 0.1516 29.3316 0 0.1516 0 0)
("M5" 0.0366 0.1516 33.4714 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x4" "CE1" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineDiodeProtection "SRAM2RW128x4" "CE1" '(0.6)
defineHierAntennaProp "SRAM2RW128x4" "CE1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0342 0.28846 3.81335 0 0.28846 0 0)
("M5" 0.0342 0.1516 12.247 0 0.1516 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x4" "WEB2" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineDiodeProtection "SRAM2RW128x4" "WEB2" '(0.6)
defineHierAntennaProp "SRAM2RW128x4" "WEB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1461 1.55662 1.03834 0 1.55662 0 0)
("M3" 0.1461 0.1516 11.692 0 0.1516 0 0)
("M4" 0.1461 0.1516 12.7289 0 0.1516 0 0)
("M5" 0.1461 0.1516 13.7656 0 0.1516 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x4" "VDD" '(0 0 0 0 3.0816 3.0816 3.0816 3.0816 3.0816 3.0816)
defineDiodeProtection "SRAM2RW128x4" "VDD" '(0 0 0 0 115.9645 115.9645 115.9645 115.9645 115.9645 115.9645)
defineHierAntennaProp "SRAM2RW128x4" "VDD" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 3.0816 2274.78 29.0978 0 2274.78 0 0)
("M6" 3.0816 0 0 0 0 0 0)
("M7" 3.0816 0 0 0 0 0 0)
("M8" 3.0816 0 0 0 0 0 0)
("M9" 3.0816 0 0 0 0 0 0)
("MRDL" 3.0816 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x4" "VSS" '(0 0 0 0 5.1498 5.1498 5.1498 5.1498 5.1498 5.1498)
defineDiodeProtection "SRAM2RW128x4" "VSS" '(0 0 0 0 103.8101 103.8101 103.8101 103.8101 103.8101 103.8101)
defineHierAntennaProp "SRAM2RW128x4" "VSS" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 5.1498 2274.73 86.3142 0 2274.73 0 0)
("M6" 5.1498 0 0 0 0 0 0)
("M7" 5.1498 0 0 0 0 0 0)
("M8" 5.1498 0 0 0 0 0 0)
("M9" 5.1498 0 0 0 0 0 0)
("MRDL" 5.1498 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x8" "I1[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW128x8" "I1[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x8" "I2[5]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW128x8" "I2[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x8" "I2[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW128x8" "I2[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x8" "I2[4]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW128x8" "I2[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x8" "I2[6]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW128x8" "I2[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x8" "OEB2" '(0 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434)
defineHierAntennaProp "SRAM2RW128x8" "OEB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1434 0.909292 0.966015 0 0.909292 0 0)
("M3" 0.1434 0.1516 7.30648 0 0.1516 0 0)
("M4" 0.1434 0.1516 8.36311 0 0.1516 0 0)
("M5" 0.1434 0.1516 9.41968 0 0.1516 0 0)
("M6" 0.1434 0 0 0 0 0 0)
("M7" 0.1434 0 0 0 0 0 0)
("M8" 0.1434 0 0 0 0 0 0)
("M9" 0.1434 0 0 0 0 0 0)
("MRDL" 0.1434 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x8" "WEB2" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineHierAntennaProp "SRAM2RW128x8" "WEB2" '(
("M1" 0 0.1504 0 0 0.1504 0 0)
("M2" 0.1461 1.56658 1.03833 0 1.56658 0 0)
("M3" 0.1461 0.1504 11.7602 0 0.1504 0 0)
("M4" 0.1461 0.1504 12.7888 0 0.1504 0 0)
("M5" 0.1461 0.1504 13.8173 0 0.1504 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x8" "WEB1" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineHierAntennaProp "SRAM2RW128x8" "WEB1" '(
("M1" 0 0.1582 0 0 0.1582 0 0)
("M2" 0.1461 1.57204 1.03833 0 1.57204 0 0)
("M3" 0.1461 0.1582 11.7976 0 0.1582 0 0)
("M4" 0.1461 0.1582 12.8796 0 0.1582 0 0)
("M5" 0.1461 0.1582 13.9616 0 0.1582 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x8" "O2[4]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x8" "O2[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277608 0 0 0.277608 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x8" "O2[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x8" "O2[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x8" "O2[5]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x8" "O2[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x8" "O1[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x8" "O1[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x8" "O1[7]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x8" "O1[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x8" "O1[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x8" "O1[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x8" "O1[6]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x8" "O1[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x8" "O1[4]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x8" "O1[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x8" "O1[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x8" "O1[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x8" "I1[5]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x8" "I1[5]" '(0.6)
defineHierAntennaProp "SRAM2RW128x8" "I1[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x8" "O1[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x8" "O1[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x8" "O1[5]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x8" "O1[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x8" "I1[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x8" "I1[3]" '(0.6)
defineHierAntennaProp "SRAM2RW128x8" "I1[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x8" "I1[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x8" "I1[2]" '(0.6)
defineHierAntennaProp "SRAM2RW128x8" "I1[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x8" "I1[4]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x8" "I1[4]" '(0.6)
defineHierAntennaProp "SRAM2RW128x8" "I1[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x8" "I1[6]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x8" "I1[6]" '(0.6)
defineHierAntennaProp "SRAM2RW128x8" "I1[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x8" "I1[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x8" "I1[1]" '(0.6)
defineHierAntennaProp "SRAM2RW128x8" "I1[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x8" "I1[7]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x8" "I1[7]" '(0.6)
defineHierAntennaProp "SRAM2RW128x8" "I1[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x8" "OEB1" '(0 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434)
defineDiodeProtection "SRAM2RW128x8" "OEB1" '(0.6)
defineHierAntennaProp "SRAM2RW128x8" "OEB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1434 0.915112 0.966015 0 0.915112 0 0)
("M3" 0.1434 0.1516 7.34706 0 0.1516 0 0)
("M4" 0.1434 0.1516 8.40369 0 0.1516 0 0)
("M5" 0.1434 0.1516 9.46026 0 0.1516 0 0)
("M6" 0.1434 0 0 0 0 0 0)
("M7" 0.1434 0 0 0 0 0 0)
("M8" 0.1434 0 0 0 0 0 0)
("M9" 0.1434 0 0 0 0 0 0)
("MRDL" 0.1434 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x8" "A2[6]" '(0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x8" "A2[6]" '(0.6)
defineHierAntennaProp "SRAM2RW128x8" "A2[6]" '(
("M1" 0.021 0.97567 0 0 0.97567 0 0)
("M2" 0.021 0.1504 46.4574 0 0.1504 0 0)
("M3" 0.021 0.1504 53.6157 0 0.1504 0 0)
("M4" 0.021 0.1504 60.7736 0 0.1504 0 0)
("M5" 0.021 0.1504 67.931 0 0.1504 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x8" "A2[5]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW128x8" "A2[5]" '(0.6)
defineHierAntennaProp "SRAM2RW128x8" "A2[5]" '(
("M1" 0.0366 0.770218 0 0 0.770218 0 0)
("M2" 0.0366 0.1504 21.0428 0 0.1504 0 0)
("M3" 0.0366 0.1504 25.1504 0 0.1504 0 0)
("M4" 0.0366 0.1504 29.2578 0 0.1504 0 0)
("M5" 0.0366 0.1504 33.3648 0 0.1504 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x8" "A2[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW128x8" "A2[0]" '(0.6)
defineHierAntennaProp "SRAM2RW128x8" "A2[0]" '(
("M1" 0.0366 0.770218 0 0 0.770218 0 0)
("M2" 0.0366 0.1504 21.0428 0 0.1504 0 0)
("M3" 0.0366 0.1504 25.1504 0 0.1504 0 0)
("M4" 0.0366 0.1504 29.2578 0 0.1504 0 0)
("M5" 0.0366 0.1504 33.3648 0 0.1504 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x8" "A2[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW128x8" "A2[1]" '(0.6)
defineHierAntennaProp "SRAM2RW128x8" "A2[1]" '(
("M1" 0.0366 0.770218 0 0 0.770218 0 0)
("M2" 0.0366 0.1504 21.0428 0 0.1504 0 0)
("M3" 0.0366 0.1504 25.1504 0 0.1504 0 0)
("M4" 0.0366 0.1504 29.2578 0 0.1504 0 0)
("M5" 0.0366 0.1504 33.3648 0 0.1504 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x8" "A2[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW128x8" "A2[2]" '(0.6)
defineHierAntennaProp "SRAM2RW128x8" "A2[2]" '(
("M1" 0.0366 0.770218 0 0 0.770218 0 0)
("M2" 0.0366 0.1504 21.0428 0 0.1504 0 0)
("M3" 0.0366 0.1504 25.1504 0 0.1504 0 0)
("M4" 0.0366 0.1504 29.2578 0 0.1504 0 0)
("M5" 0.0366 0.1504 33.3648 0 0.1504 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x8" "A2[3]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW128x8" "A2[3]" '(0.6)
defineHierAntennaProp "SRAM2RW128x8" "A2[3]" '(
("M1" 0.0366 0.770218 0 0 0.770218 0 0)
("M2" 0.0366 0.1504 21.0428 0 0.1504 0 0)
("M3" 0.0366 0.1504 25.1504 0 0.1504 0 0)
("M4" 0.0366 0.1504 29.2578 0 0.1504 0 0)
("M5" 0.0366 0.1504 33.3648 0 0.1504 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x8" "A2[4]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW128x8" "A2[4]" '(0.6)
defineHierAntennaProp "SRAM2RW128x8" "A2[4]" '(
("M1" 0.0366 0.770218 0 0 0.770218 0 0)
("M2" 0.0366 0.1504 21.0428 0 0.1504 0 0)
("M3" 0.0366 0.1504 25.1504 0 0.1504 0 0)
("M4" 0.0366 0.1504 29.2578 0 0.1504 0 0)
("M5" 0.0366 0.1504 33.3648 0 0.1504 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x8" "CE2" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineDiodeProtection "SRAM2RW128x8" "CE2" '(0.6)
defineHierAntennaProp "SRAM2RW128x8" "CE2" '(
("M1" 0 0.1504 0 0 0.1504 0 0)
("M2" 0 0.1504 0 0 0.1504 0 0)
("M3" 0 0.1504 0 0 0.1504 0 0)
("M4" 0.0342 0.30832 3.47689 0 0.30832 0 0)
("M5" 0.0342 0.1504 12.4913 0 0.1504 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x8" "CSB2" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW128x8" "CSB2" '(0.6)
defineHierAntennaProp "SRAM2RW128x8" "CSB2" '(
("M1" 0 0.1504 0 0 0.1504 0 0)
("M2" 0 0.1504 0 0 0.1504 0 0)
("M3" 0 0.1504 0 0 0.1504 0 0)
("M4" 0.0366 0.406 1.96052 0 0.406 0 0)
("M5" 0.0366 0.1504 13.0526 0 0.1504 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x8" "I2[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x8" "I2[3]" '(0.6)
defineHierAntennaProp "SRAM2RW128x8" "I2[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x8" "O2[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x8" "O2[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x8" "I2[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x8" "I2[1]" '(0.6)
defineHierAntennaProp "SRAM2RW128x8" "I2[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x8" "I2[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x8" "I2[0]" '(0.6)
defineHierAntennaProp "SRAM2RW128x8" "I2[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x8" "I2[7]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x8" "I2[7]" '(0.6)
defineHierAntennaProp "SRAM2RW128x8" "I2[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x8" "O2[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x8" "O2[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x8" "O2[7]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x8" "O2[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x8" "O2[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x8" "O2[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x8" "O2[6]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x8" "O2[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x8" "A1[5]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW128x8" "A1[5]" '(0.6)
defineHierAntennaProp "SRAM2RW128x8" "A1[5]" '(
("M1" 0.0366 0.886088 0 0 0.886088 0 0)
("M2" 0.0366 0.1504 24.2084 0 0.1504 0 0)
("M3" 0.0366 0.1504 28.3159 0 0.1504 0 0)
("M4" 0.0366 0.1504 32.423 0 0.1504 0 0)
("M5" 0.0366 0.1504 36.5299 0 0.1504 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x8" "A1[3]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW128x8" "A1[3]" '(0.6)
defineHierAntennaProp "SRAM2RW128x8" "A1[3]" '(
("M1" 0.0366 0.770218 0 0 0.770218 0 0)
("M2" 0.0366 0.1504 21.0428 0 0.1504 0 0)
("M3" 0.0366 0.1504 25.1504 0 0.1504 0 0)
("M4" 0.0366 0.1504 29.2578 0 0.1504 0 0)
("M5" 0.0366 0.1504 33.3648 0 0.1504 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x8" "A1[4]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW128x8" "A1[4]" '(0.6)
defineHierAntennaProp "SRAM2RW128x8" "A1[4]" '(
("M1" 0.0366 0.770218 0 0 0.770218 0 0)
("M2" 0.0366 0.1504 21.0428 0 0.1504 0 0)
("M3" 0.0366 0.1504 25.1504 0 0.1504 0 0)
("M4" 0.0366 0.1504 29.2578 0 0.1504 0 0)
("M5" 0.0366 0.1504 33.3648 0 0.1504 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x8" "A1[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW128x8" "A1[1]" '(0.6)
defineHierAntennaProp "SRAM2RW128x8" "A1[1]" '(
("M1" 0.0366 0.770218 0 0 0.770218 0 0)
("M2" 0.0366 0.1504 21.0428 0 0.1504 0 0)
("M3" 0.0366 0.1504 25.1504 0 0.1504 0 0)
("M4" 0.0366 0.1504 29.2578 0 0.1504 0 0)
("M5" 0.0366 0.1504 33.3648 0 0.1504 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x8" "A1[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW128x8" "A1[2]" '(0.6)
defineHierAntennaProp "SRAM2RW128x8" "A1[2]" '(
("M1" 0.0366 0.770218 0 0 0.770218 0 0)
("M2" 0.0366 0.1504 21.0428 0 0.1504 0 0)
("M3" 0.0366 0.1504 25.1504 0 0.1504 0 0)
("M4" 0.0366 0.1504 29.2578 0 0.1504 0 0)
("M5" 0.0366 0.1504 33.3648 0 0.1504 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x8" "A1[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW128x8" "A1[0]" '(0.6)
defineHierAntennaProp "SRAM2RW128x8" "A1[0]" '(
("M1" 0.0366 0.770218 0 0 0.770218 0 0)
("M2" 0.0366 0.1504 21.0428 0 0.1504 0 0)
("M3" 0.0366 0.1504 25.1504 0 0.1504 0 0)
("M4" 0.0366 0.1504 29.2578 0 0.1504 0 0)
("M5" 0.0366 0.1504 33.3648 0 0.1504 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x8" "A1[6]" '(0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x8" "A1[6]" '(0.6)
defineHierAntennaProp "SRAM2RW128x8" "A1[6]" '(
("M1" 0.021 1.13621 0 0 1.13621 0 0)
("M2" 0.021 0.1504 54.1016 0 0.1504 0 0)
("M3" 0.021 0.1504 61.2595 0 0.1504 0 0)
("M4" 0.021 0.1504 68.4168 0 0.1504 0 0)
("M5" 0.021 0.1504 75.5737 0 0.1504 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x8" "CE1" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineDiodeProtection "SRAM2RW128x8" "CE1" '(0.6)
defineHierAntennaProp "SRAM2RW128x8" "CE1" '(
("M1" 0 0.1504 0 0 0.1504 0 0)
("M2" 0 0.1504 0 0 0.1504 0 0)
("M3" 0 0.1504 0 0 0.1504 0 0)
("M4" 0.0342 0.29884 3.80244 0 0.29884 0 0)
("M5" 0.0342 0.1504 12.5396 0 0.1504 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x8" "CSB1" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW128x8" "CSB1" '(0.6)
defineHierAntennaProp "SRAM2RW128x8" "CSB1" '(
("M1" 0 0.1504 0 0 0.1504 0 0)
("M2" 0 0.1504 0 0 0.1504 0 0)
("M3" 0 0.1504 0 0 0.1504 0 0)
("M4" 0.0366 0.423949 1.92428 0 0.423949 0 0)
("M5" 0.0366 0.1504 13.5067 0 0.1504 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x8" "VDD" '(0 0 0 0 3.0816 3.0816 3.0816 3.0816 3.0816 3.0816)
defineDiodeProtection "SRAM2RW128x8" "VDD" '(0 0 0 0 160.6936 160.6936 160.6936 160.6936 160.6936 160.6936)
defineHierAntennaProp "SRAM2RW128x8" "VDD" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 3.0816 2790.12 29.0976 0 2790.12 0 0)
("M6" 3.0816 0 0 0 0 0 0)
("M7" 3.0816 0 0 0 0 0 0)
("M8" 3.0816 0 0 0 0 0 0)
("M9" 3.0816 0 0 0 0 0 0)
("MRDL" 3.0816 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x8" "VSS" '(0 0 0 0 5.49 5.49 5.49 5.49 5.49 5.49)
defineDiodeProtection "SRAM2RW128x8" "VSS" '(0 0 0 0 161.4861 161.4861 161.4861 161.4861 161.4861 161.4861)
defineHierAntennaProp "SRAM2RW128x8" "VSS" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 5.49 2790.15 86.3141 0 2790.15 0 0)
("M6" 5.49 0 0 0 0 0 0)
("M7" 5.49 0 0 0 0 0 0)
("M8" 5.49 0 0 0 0 0 0)
("M9" 5.49 0 0 0 0 0 0)
("MRDL" 5.49 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "A2[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM2RW128x16" "A2[2]" '(
("M1" 0.0366 0.771118 0 0 0.771118 0 0)
("M2" 0.0366 0.1516 21.0674 0 0.1516 0 0)
("M3" 0.0366 0.1516 25.2078 0 0.1516 0 0)
("M4" 0.0366 0.1516 29.348 0 0.1516 0 0)
("M5" 0.0366 0.1516 33.4878 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "A2[3]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM2RW128x16" "A2[3]" '(
("M1" 0.0366 0.771118 0 0 0.771118 0 0)
("M2" 0.0366 0.1516 21.0674 0 0.1516 0 0)
("M3" 0.0366 0.1516 25.2078 0 0.1516 0 0)
("M4" 0.0366 0.1516 29.348 0 0.1516 0 0)
("M5" 0.0366 0.1516 33.4878 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "A2[4]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM2RW128x16" "A2[4]" '(
("M1" 0.0366 0.771118 0 0 0.771118 0 0)
("M2" 0.0366 0.1516 21.0674 0 0.1516 0 0)
("M3" 0.0366 0.1516 25.2078 0 0.1516 0 0)
("M4" 0.0366 0.1516 29.348 0 0.1516 0 0)
("M5" 0.0366 0.1516 33.4878 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "A2[5]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM2RW128x16" "A2[5]" '(
("M1" 0.0366 0.771118 0 0 0.771118 0 0)
("M2" 0.0366 0.1516 21.0674 0 0.1516 0 0)
("M3" 0.0366 0.1516 25.2078 0 0.1516 0 0)
("M4" 0.0366 0.1516 29.348 0 0.1516 0 0)
("M5" 0.0366 0.1516 33.4878 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "A2[6]" '(0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW128x16" "A2[6]" '(
("M1" 0.021 0.97657 0 0 0.97657 0 0)
("M2" 0.021 0.1516 46.5003 0 0.1516 0 0)
("M3" 0.021 0.1516 53.7158 0 0.1516 0 0)
("M4" 0.021 0.1516 60.9308 0 0.1516 0 0)
("M5" 0.021 0.1516 68.1454 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "VSS" '(0 0 0 0 5.49 5.49 5.49 5.49 5.49 5.49)
defineDiodeProtection "SRAM2RW128x16" "VSS" '(0 0 0 0 272.6244 272.6244 272.6244 272.6244 272.6244 272.6244)
defineHierAntennaProp "SRAM2RW128x16" "VSS" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 5.49 3838.93 86.3143 0 3838.93 0 0)
("M6" 5.49 0 0 0 0 0 0)
("M7" 5.49 0 0 0 0 0 0)
("M8" 5.49 0 0 0 0 0 0)
("M9" 5.49 0 0 0 0 0 0)
("MRDL" 5.49 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "A1[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM2RW128x16" "A1[0]" '(
("M1" 0.0366 0.771118 0 0 0.771118 0 0)
("M2" 0.0366 0.1516 21.0674 0 0.1516 0 0)
("M3" 0.0366 0.1516 25.2078 0 0.1516 0 0)
("M4" 0.0366 0.1516 29.348 0 0.1516 0 0)
("M5" 0.0366 0.1516 33.4878 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineHierAntennaProp "SRAM2RW128x16" "CSB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0 0.424789 0 0 0.424789 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
)
defineGateSize "SRAM2RW128x16" "CE1" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineHierAntennaProp "SRAM2RW128x16" "CE1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0342 0.29968 3.80244 0 0.29968 0 0)
("M5" 0.0342 0.1516 12.5642 0 0.1516 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "VDD" '(0 0 0 0 3.0816 3.0816 3.0816 3.0816 3.0816 3.0816)
defineDiodeProtection "SRAM2RW128x16" "VDD" '(0 0 0 0 250.1519 250.1519 250.1519 250.1519 250.1519 250.1519)
defineHierAntennaProp "SRAM2RW128x16" "VDD" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 3.0816 3879.38 29.459 0 3879.38 0 0)
("M6" 3.0816 0 0 0 0 0 0)
("M7" 3.0816 0 0 0 0 0 0)
("M8" 3.0816 0 0 0 0 0 0)
("M9" 3.0816 0 0 0 0 0 0)
("MRDL" 3.0816 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x16" "O1[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x16" "O1[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "I1[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW128x16" "I1[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x16" "O1[13]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x16" "O1[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x16" "O1[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x16" "O1[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "I1[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x16" "I1[3]" '(0.6)
defineHierAntennaProp "SRAM2RW128x16" "I1[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x16" "O1[10]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x16" "O1[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "I1[10]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x16" "I1[10]" '(0.6)
defineHierAntennaProp "SRAM2RW128x16" "I1[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x16" "O1[8]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x16" "O1[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "I1[8]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x16" "I1[8]" '(0.6)
defineHierAntennaProp "SRAM2RW128x16" "I1[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "OEB2" '(0 0.2682 0.2682 0.2682 0.2682 0.2682 0.2682 0.2682 0.2682 0.2682)
defineDiodeProtection "SRAM2RW128x16" "OEB2" '(0.6)
defineHierAntennaProp "SRAM2RW128x16" "OEB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.2682 1.564 0.96602 0 1.564 0 0)
("M3" 0.2682 0.1516 6.79704 0 0.1516 0 0)
("M4" 0.2682 0.1516 7.3618 0 0.1516 0 0)
("M5" 0.2682 0.1516 7.92653 0 0.1516 0 0)
("M6" 0.2682 0 0 0 0 0 0)
("M7" 0.2682 0 0 0 0 0 0)
("M8" 0.2682 0 0 0 0 0 0)
("M9" 0.2682 0 0 0 0 0 0)
("MRDL" 0.2682 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "OEB1" '(0 0.2682 0.2682 0.2682 0.2682 0.2682 0.2682 0.2682 0.2682 0.2682)
defineDiodeProtection "SRAM2RW128x16" "OEB1" '(0.6)
defineHierAntennaProp "SRAM2RW128x16" "OEB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.2682 1.56982 0.96602 0 1.56982 0 0)
("M3" 0.2682 0.1516 6.81874 0 0.1516 0 0)
("M4" 0.2682 0.1516 7.3835 0 0.1516 0 0)
("M5" 0.2682 0.1516 7.94823 0 0.1516 0 0)
("M6" 0.2682 0 0 0 0 0 0)
("M7" 0.2682 0 0 0 0 0 0)
("M8" 0.2682 0 0 0 0 0 0)
("M9" 0.2682 0 0 0 0 0 0)
("MRDL" 0.2682 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "WEB1" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineDiodeProtection "SRAM2RW128x16" "WEB1" '(0.6)
defineHierAntennaProp "SRAM2RW128x16" "WEB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1461 1.56742 1.03833 0 1.56742 0 0)
("M3" 0.1461 0.1516 11.766 0 0.1516 0 0)
("M4" 0.1461 0.1516 12.8028 0 0.1516 0 0)
("M5" 0.1461 0.1516 13.8395 0 0.1516 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "WEB2" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineDiodeProtection "SRAM2RW128x16" "WEB2" '(0.6)
defineHierAntennaProp "SRAM2RW128x16" "WEB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1461 1.56742 1.03833 0 1.56742 0 0)
("M3" 0.1461 0.1516 11.766 0 0.1516 0 0)
("M4" 0.1461 0.1516 12.8028 0 0.1516 0 0)
("M5" 0.1461 0.1516 13.8395 0 0.1516 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x16" "O2[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x16" "O2[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "I1[7]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x16" "I1[7]" '(0.6)
defineHierAntennaProp "SRAM2RW128x16" "I1[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x16" "O1[12]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x16" "O1[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "I1[12]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x16" "I1[12]" '(0.6)
defineHierAntennaProp "SRAM2RW128x16" "I1[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x16" "O1[11]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x16" "O1[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "I1[11]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x16" "I1[11]" '(0.6)
defineHierAntennaProp "SRAM2RW128x16" "I1[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x16" "O1[4]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x16" "O1[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "I1[4]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x16" "I1[4]" '(0.6)
defineHierAntennaProp "SRAM2RW128x16" "I1[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "I1[13]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x16" "I1[13]" '(0.6)
defineHierAntennaProp "SRAM2RW128x16" "I1[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x16" "O1[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x16" "O1[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "I1[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x16" "I1[1]" '(0.6)
defineHierAntennaProp "SRAM2RW128x16" "I1[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x16" "O1[5]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x16" "O1[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "I1[5]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x16" "I1[5]" '(0.6)
defineHierAntennaProp "SRAM2RW128x16" "I1[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x16" "O1[7]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x16" "O1[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x16" "O1[9]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x16" "O1[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "I1[9]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x16" "I1[9]" '(0.6)
defineHierAntennaProp "SRAM2RW128x16" "I1[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x16" "O1[14]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x16" "O1[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "I1[14]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x16" "I1[14]" '(0.6)
defineHierAntennaProp "SRAM2RW128x16" "I1[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "I2[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x16" "I2[0]" '(0.6)
defineHierAntennaProp "SRAM2RW128x16" "I2[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x16" "O2[13]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x16" "O2[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "I2[13]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x16" "I2[13]" '(0.6)
defineHierAntennaProp "SRAM2RW128x16" "I2[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x16" "O2[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x16" "O2[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "I2[14]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x16" "I2[14]" '(0.6)
defineHierAntennaProp "SRAM2RW128x16" "I2[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x16" "O2[9]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x16" "O2[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "I2[9]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x16" "I2[9]" '(0.6)
defineHierAntennaProp "SRAM2RW128x16" "I2[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x16" "O2[14]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x16" "O2[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "I2[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x16" "I2[3]" '(0.6)
defineHierAntennaProp "SRAM2RW128x16" "I2[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x16" "O2[10]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x16" "O2[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "I2[10]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x16" "I2[10]" '(0.6)
defineHierAntennaProp "SRAM2RW128x16" "I2[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x16" "O2[8]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x16" "O2[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "I2[8]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x16" "I2[8]" '(0.6)
defineHierAntennaProp "SRAM2RW128x16" "I2[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x16" "O1[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x16" "O1[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "I1[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x16" "I1[2]" '(0.6)
defineHierAntennaProp "SRAM2RW128x16" "I1[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x16" "O1[15]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x16" "O1[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "I1[15]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x16" "I1[15]" '(0.6)
defineHierAntennaProp "SRAM2RW128x16" "I1[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x16" "O1[6]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x16" "O1[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "I1[6]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x16" "I1[6]" '(0.6)
defineHierAntennaProp "SRAM2RW128x16" "I1[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "I2[15]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x16" "I2[15]" '(0.6)
defineHierAntennaProp "SRAM2RW128x16" "I2[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1514 62.3746 0 0.1514 0 0)
("M5" 0.021 0.1514 69.5795 0 0.1514 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x16" "O2[6]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x16" "O2[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "I2[6]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x16" "I2[6]" '(0.6)
defineHierAntennaProp "SRAM2RW128x16" "I2[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "I2[4]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x16" "I2[4]" '(0.6)
defineHierAntennaProp "SRAM2RW128x16" "I2[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x16" "O2[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x16" "O2[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "I2[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x16" "I2[2]" '(0.6)
defineHierAntennaProp "SRAM2RW128x16" "I2[2]" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x16" "O2[15]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x16" "O2[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x16" "O2[4]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x16" "O2[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x16" "O2[12]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x16" "O2[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "I2[12]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x16" "I2[12]" '(0.6)
defineHierAntennaProp "SRAM2RW128x16" "I2[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x16" "O2[11]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x16" "O2[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "I2[11]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x16" "I2[11]" '(0.6)
defineHierAntennaProp "SRAM2RW128x16" "I2[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x16" "O2[5]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x16" "O2[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "I2[5]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x16" "I2[5]" '(0.6)
defineHierAntennaProp "SRAM2RW128x16" "I2[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x16" "O2[7]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x16" "O2[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "I2[7]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x16" "I2[7]" '(0.6)
defineHierAntennaProp "SRAM2RW128x16" "I2[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "I2[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x16" "I2[1]" '(0.6)
defineHierAntennaProp "SRAM2RW128x16" "I2[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x16" "O2[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x16" "O2[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "A1[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW128x16" "A1[1]" '(0.6)
defineHierAntennaProp "SRAM2RW128x16" "A1[1]" '(
("M1" 0.0366 0.771118 0 0 0.771118 0 0)
("M2" 0.0366 0.1516 21.0674 0 0.1516 0 0)
("M3" 0.0366 0.1516 25.2078 0 0.1516 0 0)
("M4" 0.0366 0.1516 29.348 0 0.1516 0 0)
("M5" 0.0366 0.1516 33.4878 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "A1[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW128x16" "A1[2]" '(0.6)
defineHierAntennaProp "SRAM2RW128x16" "A1[2]" '(
("M1" 0.0366 0.771118 0 0 0.771118 0 0)
("M2" 0.0366 0.1516 21.0674 0 0.1516 0 0)
("M3" 0.0366 0.1516 25.2078 0 0.1516 0 0)
("M4" 0.0366 0.1516 29.348 0 0.1516 0 0)
("M5" 0.0366 0.1516 33.4878 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "A1[3]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW128x16" "A1[3]" '(0.6)
defineHierAntennaProp "SRAM2RW128x16" "A1[3]" '(
("M1" 0.0366 0.771118 0 0 0.771118 0 0)
("M2" 0.0366 0.1516 21.0674 0 0.1516 0 0)
("M3" 0.0366 0.1516 25.2078 0 0.1516 0 0)
("M4" 0.0366 0.1516 29.348 0 0.1516 0 0)
("M5" 0.0366 0.1516 33.4878 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "A1[4]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW128x16" "A1[4]" '(0.6)
defineHierAntennaProp "SRAM2RW128x16" "A1[4]" '(
("M1" 0.0366 0.771118 0 0 0.771118 0 0)
("M2" 0.0366 0.1516 21.0674 0 0.1516 0 0)
("M3" 0.0366 0.1516 25.2078 0 0.1516 0 0)
("M4" 0.0366 0.1516 29.348 0 0.1516 0 0)
("M5" 0.0366 0.1516 33.4878 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "A1[5]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW128x16" "A1[5]" '(0.6)
defineHierAntennaProp "SRAM2RW128x16" "A1[5]" '(
("M1" 0.0366 0.886928 0 0 0.886928 0 0)
("M2" 0.0366 0.1516 24.2314 0 0.1516 0 0)
("M3" 0.0366 0.1516 28.3716 0 0.1516 0 0)
("M4" 0.0366 0.1516 32.5115 0 0.1516 0 0)
("M5" 0.0366 0.1516 36.6512 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "A1[6]" '(0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x16" "A1[6]" '(0.6)
defineHierAntennaProp "SRAM2RW128x16" "A1[6]" '(
("M1" 0.021 1.13705 0 0 1.13705 0 0)
("M2" 0.021 0.1516 54.1417 0 0.1516 0 0)
("M3" 0.021 0.1516 61.3567 0 0.1516 0 0)
("M4" 0.021 0.1516 68.5712 0 0.1516 0 0)
("M5" 0.021 0.1516 75.7852 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "CE2" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineDiodeProtection "SRAM2RW128x16" "CE2" '(0.6)
defineHierAntennaProp "SRAM2RW128x16" "CE2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0342 0.30916 3.47688 0 0.30916 0 0)
("M5" 0.0342 0.1516 12.5158 0 0.1516 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "CSB2" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW128x16" "CSB2" '(0.6)
defineHierAntennaProp "SRAM2RW128x16" "CSB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0366 0.40684 1.96052 0 0.40684 0 0)
("M5" 0.0366 0.1516 13.0755 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "A2[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW128x16" "A2[0]" '(0.6)
defineHierAntennaProp "SRAM2RW128x16" "A2[0]" '(
("M1" 0.0366 0.771118 0 0 0.771118 0 0)
("M2" 0.0366 0.1516 21.0674 0 0.1516 0 0)
("M3" 0.0366 0.1516 25.2078 0 0.1516 0 0)
("M4" 0.0366 0.1516 29.348 0 0.1516 0 0)
("M5" 0.0366 0.1516 33.4878 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x16" "A2[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW128x16" "A2[1]" '(0.6)
defineHierAntennaProp "SRAM2RW128x16" "A2[1]" '(
("M1" 0.0366 0.771118 0 0 0.771118 0 0)
("M2" 0.0366 0.1516 21.0674 0 0.1516 0 0)
("M3" 0.0366 0.1516 25.2078 0 0.1516 0 0)
("M4" 0.0366 0.1516 29.348 0 0.1516 0 0)
("M5" 0.0366 0.1516 33.4878 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I1[14]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW128x32" "I1[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I1[11]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW128x32" "I1[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I1[28]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW128x32" "I1[28]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I1[25]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW128x32" "I1[25]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I1[31]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW128x32" "I1[31]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I1[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW128x32" "I1[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I1[23]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW128x32" "I1[23]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O1[31]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O1[31]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O1[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O1[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O1[23]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O1[23]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I1[26]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I1[26]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I1[26]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.29343 1.24826 0 1.29343 0 0)
("M4" 0.021 0.1516 62.836 0 0.1516 0 0)
("M5" 0.021 0.1516 70.0504 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O1[25]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O1[25]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O1[29]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O1[29]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O1[22]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O1[22]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O1[26]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O1[26]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I1[29]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I1[29]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I1[29]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I1[22]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I1[22]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I1[22]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O1[15]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O1[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I2[8]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I2[8]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I2[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O1[6]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O1[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O1[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O1[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I1[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I1[2]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I1[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I1[6]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I1[6]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I1[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O1[14]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O1[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O1[30]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O1[30]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O1[19]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O1[19]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I1[5]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I1[5]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I1[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I1[30]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I1[30]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I1[30]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I1[19]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I1[19]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I1[19]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O1[13]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O1[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I1[13]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I1[13]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I1[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O1[5]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O1[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O1[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O1[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I1[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I1[1]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I1[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O1[4]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O1[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O1[11]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O1[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "A2[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW128x32" "A2[1]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "A2[1]" '(
("M1" 0.0366 0.771118 0 0 0.771118 0 0)
("M2" 0.0366 0.1516 21.0674 0 0.1516 0 0)
("M3" 0.0366 0.1516 25.2078 0 0.1516 0 0)
("M4" 0.0366 0.1516 29.348 0 0.1516 0 0)
("M5" 0.0366 0.1516 33.4878 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "A1[6]" '(0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "A1[6]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "A1[6]" '(
("M1" 0.021 1.13705 0 0 1.13705 0 0)
("M2" 0.021 0.1516 54.1417 0 0.1516 0 0)
("M3" 0.021 0.1516 61.3567 0 0.1516 0 0)
("M4" 0.021 0.1516 68.5712 0 0.1516 0 0)
("M5" 0.021 0.1516 75.7852 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "A2[5]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW128x32" "A2[5]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "A2[5]" '(
("M1" 0.0366 0.771118 0 0 0.771118 0 0)
("M2" 0.0366 0.1516 21.0674 0 0.1516 0 0)
("M3" 0.0366 0.1516 25.2078 0 0.1516 0 0)
("M4" 0.0366 0.1516 29.348 0 0.1516 0 0)
("M5" 0.0366 0.1516 33.4878 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I2[7]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I2[7]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I2[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O2[18]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O2[18]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O2[7]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O2[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O2[24]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O2[24]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I2[17]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I2[17]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I2[17]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O2[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O2[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O2[9]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O2[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O2[10]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O2[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I2[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I2[3]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I2[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I2[9]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I2[9]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I2[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I2[10]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I2[10]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I2[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O2[17]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O2[17]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O2[16]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O2[16]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I2[16]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I2[16]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I2[16]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O2[12]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O2[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O2[8]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O2[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I2[12]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I2[12]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I2[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "A1[4]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW128x32" "A1[4]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "A1[4]" '(
("M1" 0.0366 0.771118 0 0 0.771118 0 0)
("M2" 0.0366 0.1516 21.0674 0 0.1516 0 0)
("M3" 0.0366 0.1516 25.2078 0 0.1516 0 0)
("M4" 0.0366 0.1516 29.348 0 0.1516 0 0)
("M5" 0.0366 0.1516 33.4878 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "A1[3]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW128x32" "A1[3]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "A1[3]" '(
("M1" 0.0366 0.771118 0 0 0.771118 0 0)
("M2" 0.0366 0.1516 21.0674 0 0.1516 0 0)
("M3" 0.0366 0.1516 25.2078 0 0.1516 0 0)
("M4" 0.0366 0.1516 29.348 0 0.1516 0 0)
("M5" 0.0366 0.1516 33.4878 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "A1[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW128x32" "A1[2]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "A1[2]" '(
("M1" 0.0366 0.771118 0 0 0.771118 0 0)
("M2" 0.0366 0.1516 21.0674 0 0.1516 0 0)
("M3" 0.0366 0.1516 25.2078 0 0.1516 0 0)
("M4" 0.0366 0.1516 29.348 0 0.1516 0 0)
("M5" 0.0366 0.1516 33.4878 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "A1[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW128x32" "A1[1]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "A1[1]" '(
("M1" 0.0366 0.771118 0 0 0.771118 0 0)
("M2" 0.0366 0.1516 21.0674 0 0.1516 0 0)
("M3" 0.0366 0.1516 25.2078 0 0.1516 0 0)
("M4" 0.0366 0.1516 29.348 0 0.1516 0 0)
("M5" 0.0366 0.1516 33.4878 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "A1[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW128x32" "A1[0]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "A1[0]" '(
("M1" 0.0366 0.771118 0 0 0.771118 0 0)
("M2" 0.0366 0.1516 21.0674 0 0.1516 0 0)
("M3" 0.0366 0.1516 25.2078 0 0.1516 0 0)
("M4" 0.0366 0.1516 29.348 0 0.1516 0 0)
("M5" 0.0366 0.1516 33.4878 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "CSB2" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW128x32" "CSB2" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "CSB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0366 0.40684 1.96052 0 0.40684 0 0)
("M5" 0.0366 0.1516 13.0755 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "CE2" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineDiodeProtection "SRAM2RW128x32" "CE2" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "CE2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0342 0.30916 3.47688 0 0.30916 0 0)
("M5" 0.0342 0.1516 12.5158 0 0.1516 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "A2[6]" '(0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "A2[6]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "A2[6]" '(
("M1" 0.021 0.97657 0 0 0.97657 0 0)
("M2" 0.021 0.1516 46.5003 0 0.1516 0 0)
("M3" 0.021 0.1516 53.7158 0 0.1516 0 0)
("M4" 0.021 0.1516 60.9308 0 0.1516 0 0)
("M5" 0.021 0.1516 68.1454 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "A2[4]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW128x32" "A2[4]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "A2[4]" '(
("M1" 0.0366 0.771118 0 0 0.771118 0 0)
("M2" 0.0366 0.1516 21.0674 0 0.1516 0 0)
("M3" 0.0366 0.1516 25.2078 0 0.1516 0 0)
("M4" 0.0366 0.1516 29.348 0 0.1516 0 0)
("M5" 0.0366 0.1516 33.4878 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "A2[3]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW128x32" "A2[3]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "A2[3]" '(
("M1" 0.0366 0.771118 0 0 0.771118 0 0)
("M2" 0.0366 0.1516 21.0674 0 0.1516 0 0)
("M3" 0.0366 0.1516 25.2078 0 0.1516 0 0)
("M4" 0.0366 0.1516 29.348 0 0.1516 0 0)
("M5" 0.0366 0.1516 33.4878 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "A2[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW128x32" "A2[2]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "A2[2]" '(
("M1" 0.0366 0.771118 0 0 0.771118 0 0)
("M2" 0.0366 0.1516 21.0674 0 0.1516 0 0)
("M3" 0.0366 0.1516 25.2078 0 0.1516 0 0)
("M4" 0.0366 0.1516 29.348 0 0.1516 0 0)
("M5" 0.0366 0.1516 33.4878 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "A2[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW128x32" "A2[0]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "A2[0]" '(
("M1" 0.0366 0.771118 0 0 0.771118 0 0)
("M2" 0.0366 0.1516 21.0674 0 0.1516 0 0)
("M3" 0.0366 0.1516 25.2078 0 0.1516 0 0)
("M4" 0.0366 0.1516 29.348 0 0.1516 0 0)
("M5" 0.0366 0.1516 33.4878 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "VSS" '(0 0 0 0 5.49 5.49 5.49 5.49 5.49 5.49)
defineDiodeProtection "SRAM2RW128x32" "VSS" '(0 0 0 0 494.901 494.901 494.901 494.901 494.901 494.901)
defineHierAntennaProp "SRAM2RW128x32" "VSS" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 5.49 6194.6 82.7749 0 6194.6 0 0)
("M6" 5.49 0 0 0 0 0 0)
("M7" 5.49 0 0 0 0 0 0)
("M8" 5.49 0 0 0 0 0 0)
("M9" 5.49 0 0 0 0 0 0)
("MRDL" 5.49 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "CE1" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineDiodeProtection "SRAM2RW128x32" "CE1" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "CE1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0342 0.29968 3.80244 0 0.29968 0 0)
("M5" 0.0342 0.1516 12.5642 0 0.1516 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "WEB2" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineDiodeProtection "SRAM2RW128x32" "WEB2" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "WEB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1461 1.56742 1.03833 0 1.56742 0 0)
("M3" 0.1461 0.1516 11.766 0 0.1516 0 0)
("M4" 0.1461 0.1516 12.8028 0 0.1516 0 0)
("M5" 0.1461 0.1516 13.8395 0 0.1516 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "A1[5]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW128x32" "A1[5]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "A1[5]" '(
("M1" 0.0366 0.771118 0 0 0.771118 0 0)
("M2" 0.0366 0.1516 21.0674 0 0.1516 0 0)
("M3" 0.0366 0.1516 25.2078 0 0.1516 0 0)
("M4" 0.0366 0.1516 29.348 0 0.1516 0 0)
("M5" 0.0366 0.1516 33.4878 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "CSB1" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW128x32" "CSB1" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "CSB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0366 0.424789 1.92429 0 0.424789 0 0)
("M5" 0.0366 0.1516 13.5297 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "VDD" '(0 0 0 0 3.0816 3.0816 3.0816 3.0816 3.0816 3.0816)
defineDiodeProtection "SRAM2RW128x32" "VDD" '(0 0 0 0 429.0684 429.0684 429.0684 429.0684 429.0684 429.0684)
defineHierAntennaProp "SRAM2RW128x32" "VDD" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 3.0816 6194.14 29.4754 0 6194.14 0 0)
("M6" 3.0816 0 0 0 0 0 0)
("M7" 3.0816 0 0 0 0 0 0)
("M8" 3.0816 0 0 0 0 0 0)
("M9" 3.0816 0 0 0 0 0 0)
("MRDL" 3.0816 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O1[16]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O1[16]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O1[10]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O1[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I2[13]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I2[13]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I2[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I1[4]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I1[4]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I1[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "WEB1" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineDiodeProtection "SRAM2RW128x32" "WEB1" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "WEB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1461 1.56742 1.03833 0 1.56742 0 0)
("M3" 0.1461 0.1516 11.766 0 0.1516 0 0)
("M4" 0.1461 0.1516 12.8028 0 0.1516 0 0)
("M5" 0.1461 0.1516 13.8395 0 0.1516 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I2[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I2[0]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I2[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I2[23]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I2[23]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I2[23]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O2[26]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O2[26]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I2[21]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I2[21]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I2[21]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I2[22]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I2[22]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I2[22]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I2[29]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I2[29]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I2[29]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O2[21]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O2[21]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O2[29]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O2[29]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O2[22]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O2[22]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O2[15]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O2[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I2[27]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I2[27]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I2[27]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I2[15]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I2[15]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I2[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O2[20]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O2[20]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O2[27]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O2[27]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I2[24]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I2[24]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I2[24]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I2[20]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I2[20]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I2[20]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I2[18]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I2[18]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I2[18]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I1[15]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I1[15]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I1[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I2[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I2[1]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I2[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "OEB1" '(0 0.5178 0.5178 0.5178 0.5178 0.5178 0.5178 0.5178 0.5178 0.5178)
defineDiodeProtection "SRAM2RW128x32" "OEB1" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "OEB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.5178 2.8876 0.966022 0 2.8876 0 0)
("M3" 0.5178 0.1516 6.54226 0 0.1516 0 0)
("M4" 0.5178 0.1516 6.83459 0 0.1516 0 0)
("M5" 0.5178 0.1516 7.12689 0 0.1516 0 0)
("M6" 0.5178 0 0 0 0 0 0)
("M7" 0.5178 0 0 0 0 0 0)
("M8" 0.5178 0 0 0 0 0 0)
("M9" 0.5178 0 0 0 0 0 0)
("MRDL" 0.5178 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I2[5]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I2[5]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I2[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I2[30]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I2[30]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I2[30]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O2[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O2[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O2[4]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O2[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O2[11]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O2[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O2[28]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O2[28]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I2[25]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I2[25]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I2[25]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I2[4]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I2[4]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I2[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I2[11]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I2[11]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I2[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I2[28]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I2[28]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I2[28]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O2[31]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O2[31]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O2[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O2[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O2[23]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O2[23]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O2[25]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O2[25]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I2[26]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I2[26]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I2[26]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I2[31]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I2[31]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I2[31]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I1[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I1[3]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I1[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O1[12]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O1[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O1[8]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O1[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O2[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O2[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I1[8]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I1[8]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I1[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I1[16]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I1[16]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I1[16]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I1[12]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I1[12]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I1[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O2[19]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O2[19]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O2[14]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O2[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O2[6]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O2[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I2[19]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I2[19]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I2[19]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I2[14]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I2[14]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I2[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I2[6]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I2[6]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I2[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I2[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I2[2]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I2[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O2[13]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O2[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O2[5]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O2[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O2[30]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O2[30]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O1[21]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O1[21]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I1[27]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I1[27]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I1[27]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "OEB2" '(0 0.5178 0.5178 0.5178 0.5178 0.5178 0.5178 0.5178 0.5178 0.5178)
defineDiodeProtection "SRAM2RW128x32" "OEB2" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "OEB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.5178 2.88178 0.966022 0 2.88178 0 0)
("M3" 0.5178 0.1516 6.53102 0 0.1516 0 0)
("M4" 0.5178 0.1516 6.82335 0 0.1516 0 0)
("M5" 0.5178 0.1516 7.11566 0 0.1516 0 0)
("M6" 0.5178 0 0 0 0 0 0)
("M7" 0.5178 0 0 0 0 0 0)
("M8" 0.5178 0 0 0 0 0 0)
("M9" 0.5178 0 0 0 0 0 0)
("MRDL" 0.5178 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I1[21]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I1[21]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I1[21]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I1[20]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I1[20]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I1[20]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O1[24]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O1[24]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O1[20]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O1[20]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I1[24]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I1[24]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I1[24]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O1[27]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O1[27]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O1[18]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O1[18]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O1[7]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O1[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I1[17]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I1[17]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I1[17]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I1[18]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I1[18]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I1[18]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I1[7]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I1[7]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I1[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I1[10]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I1[10]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I1[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW128x32" "I1[9]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW128x32" "I1[9]" '(0.6)
defineHierAntennaProp "SRAM2RW128x32" "I1[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O1[17]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O1[17]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O1[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O1[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O1[9]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O1[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW128x32" "O1[28]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW128x32" "O1[28]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x22" "O2[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x22" "O2[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "I2[9]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW32x22" "I2[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x22" "O2[13]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x22" "O2[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x22" "O2[5]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x22" "O2[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "I2[5]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW32x22" "I2[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "I2[16]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW32x22" "I2[16]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x22" "O1[8]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x22" "O1[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "A2[1]" '(0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM2RW32x22" "A2[1]" '(
("M1" 0 0.7849 0 0 0.7849 0 0)
("M2" 0.0366 0.26062 1.10564 0 0.26062 0 0)
("M3" 0.0366 0.1516 8.22586 0 0.1516 0 0)
("M4" 0.0366 0.1516 12.3671 0 0.1516 0 0)
("M5" 0.0366 0.1516 16.5081 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x22" "O2[11]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x22" "O2[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x22" "O1[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x22" "O1[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "I2[6]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW32x22" "I2[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "I2[18]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x22" "I2[18]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "I2[18]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "I1[16]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x22" "I1[16]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "I1[16]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x22" "O2[21]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x22" "O2[21]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x22" "O1[18]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x22" "O1[18]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "I1[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x22" "I1[2]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "I1[2]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x22" "O2[19]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x22" "O2[19]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x22" "O2[15]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x22" "O2[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "I2[19]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x22" "I2[19]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "I2[19]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x22" "O1[21]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x22" "O1[21]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x22" "O2[4]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x22" "O2[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "I2[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x22" "I2[0]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "I2[0]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "I2[4]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x22" "I2[4]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "I2[4]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "I1[17]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x22" "I1[17]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "I1[17]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x22" "O2[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x22" "O2[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "I2[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x22" "I2[2]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "I2[2]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "I2[12]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x22" "I2[12]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "I2[12]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x22" "O2[14]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x22" "O2[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x22" "O1[20]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x22" "O1[20]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "I2[14]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x22" "I2[14]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "I2[14]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x22" "O2[20]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x22" "O2[20]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x22" "O2[7]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x22" "O2[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x22" "O1[14]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x22" "O1[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x22" "O2[12]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x22" "O2[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x22" "O1[6]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x22" "O1[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x22" "O1[15]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x22" "O1[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x22" "O2[8]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x22" "O2[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x22" "O2[16]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x22" "O2[16]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x22" "O2[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x22" "O2[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "I2[8]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x22" "I2[8]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "I2[8]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "I1[12]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x22" "I1[12]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "I1[12]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x22" "O1[9]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x22" "O1[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x22" "O2[18]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x22" "O2[18]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x22" "O2[9]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x22" "O2[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x22" "O2[10]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x22" "O2[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "I1[20]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x22" "I1[20]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "I1[20]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "I2[10]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x22" "I2[10]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "I2[10]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "I1[9]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x22" "I1[9]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "I1[9]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "I1[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x22" "I1[3]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "I1[3]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "I2[21]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x22" "I2[21]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "I2[21]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x22" "O1[16]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x22" "O1[16]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "I1[8]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x22" "I1[8]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "I1[8]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x22" "O1[11]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x22" "O1[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x22" "O1[10]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x22" "O1[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "I1[14]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x22" "I1[14]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "I1[14]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "I1[11]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x22" "I1[11]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "I1[11]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x22" "O1[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x22" "O1[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x22" "O1[13]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x22" "O1[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "I1[10]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x22" "I1[10]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "I1[10]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "I1[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x22" "I1[1]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "I1[1]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x22" "O1[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x22" "O1[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x22" "O1[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x22" "O1[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "I1[5]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x22" "I1[5]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "I1[5]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x22" "O1[5]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x22" "O1[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "I1[13]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x22" "I1[13]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "I1[13]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "I1[4]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x22" "I1[4]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "I1[4]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "I1[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x22" "I1[0]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "I1[0]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "I1[7]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x22" "I1[7]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "I1[7]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "I1[6]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x22" "I1[6]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "I1[6]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "I1[15]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x22" "I1[15]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "I1[15]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "A1[2]" '(0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x22" "A1[2]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "A1[2]" '(
("M1" 0 0.822 0 0 0.822 0 0)
("M2" 0.0366 0.21412 1.10563 0 0.21412 0 0)
("M3" 0.0366 0.1516 6.95544 0 0.1516 0 0)
("M4" 0.0366 0.1516 11.0968 0 0.1516 0 0)
("M5" 0.0366 0.1516 15.2379 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "I1[18]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x22" "I1[18]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "I1[18]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "CSB2" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x22" "CSB2" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "CSB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0366 0.40684 1.96052 0 0.40684 0 0)
("M5" 0.0366 0.1516 13.0755 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "CE2" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineDiodeProtection "SRAM2RW32x22" "CE2" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "CE2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0342 0.30916 3.47688 0 0.30916 0 0)
("M5" 0.0342 0.1516 12.5158 0 0.1516 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "A2[4]" '(0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x22" "A2[4]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "A2[4]" '(
("M1" 0.021 0.97657 0 0 0.97657 0 0)
("M2" 0.021 0.1516 46.5003 0 0.1516 0 0)
("M3" 0.021 0.1516 53.7158 0 0.1516 0 0)
("M4" 0.021 0.1516 60.9308 0 0.1516 0 0)
("M5" 0.021 0.1516 68.1454 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "A2[3]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x22" "A2[3]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "A2[3]" '(
("M1" 0.0366 0.895918 0 0 0.895918 0 0)
("M2" 0.0366 0.1516 24.477 0 0.1516 0 0)
("M3" 0.0366 0.1516 28.6172 0 0.1516 0 0)
("M4" 0.0366 0.1516 32.7571 0 0.1516 0 0)
("M5" 0.0366 0.1516 36.8968 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "A2[2]" '(0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x22" "A2[2]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "A2[2]" '(
("M1" 0 0.7849 0 0 0.7849 0 0)
("M2" 0.0366 0.25462 1.10564 0 0.25462 0 0)
("M3" 0.0366 0.1516 8.06193 0 0.1516 0 0)
("M4" 0.0366 0.1516 12.2032 0 0.1516 0 0)
("M5" 0.0366 0.1516 16.3442 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "A2[0]" '(0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x22" "A2[0]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "A2[0]" '(
("M1" 0 0.7849 0 0 0.7849 0 0)
("M2" 0.0366 0.26062 1.10564 0 0.26062 0 0)
("M3" 0.0366 0.1516 8.22586 0 0.1516 0 0)
("M4" 0.0366 0.1516 12.3671 0 0.1516 0 0)
("M5" 0.0366 0.1516 16.5081 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x22" "O2[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x22" "O2[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "I2[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x22" "I2[3]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "I2[3]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "WEB2" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineDiodeProtection "SRAM2RW32x22" "WEB2" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "WEB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1461 1.56742 1.03833 0 1.56742 0 0)
("M3" 0.1461 0.1516 11.766 0 0.1516 0 0)
("M4" 0.1461 0.1516 12.8028 0 0.1516 0 0)
("M5" 0.1461 0.1516 13.8395 0 0.1516 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "WEB1" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineDiodeProtection "SRAM2RW32x22" "WEB1" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "WEB1" '(
("M1" 0 0.15352 0 0 0.15352 0 0)
("M2" 0.1461 1.56742 1.03833 0 1.56742 0 0)
("M3" 0.1461 0.15352 11.766 0 0.15352 0 0)
("M4" 0.1461 0.15352 12.8159 0 0.15352 0 0)
("M5" 0.1461 0.15352 13.8658 0 0.15352 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "OEB1" '(0 0.3618 0.3618 0.3618 0.3618 0.3618 0.3618 0.3618 0.3618 0.3618)
defineDiodeProtection "SRAM2RW32x22" "OEB1" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "OEB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.3618 2.0668 0.966022 0 2.0668 0 0)
("M3" 0.3618 0.1516 6.67813 0 0.1516 0 0)
("M4" 0.3618 0.1516 7.09668 0 0.1516 0 0)
("M5" 0.3618 0.1516 7.5152 0 0.1516 0 0)
("M6" 0.3618 0 0 0 0 0 0)
("M7" 0.3618 0 0 0 0 0 0)
("M8" 0.3618 0 0 0 0 0 0)
("M9" 0.3618 0 0 0 0 0 0)
("MRDL" 0.3618 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "I1[21]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x22" "I1[21]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "I1[21]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "OEB2" '(0 0.3618 0.3618 0.3618 0.3618 0.3618 0.3618 0.3618 0.3618 0.3618)
defineDiodeProtection "SRAM2RW32x22" "OEB2" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "OEB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.3618 2.06656 0.966022 0 2.06656 0 0)
("M3" 0.3618 0.1516 6.67746 0 0.1516 0 0)
("M4" 0.3618 0.1516 7.09601 0 0.1516 0 0)
("M5" 0.3618 0.1516 7.51453 0 0.1516 0 0)
("M6" 0.3618 0 0 0 0 0 0)
("M7" 0.3618 0 0 0 0 0 0)
("M8" 0.3618 0 0 0 0 0 0)
("M9" 0.3618 0 0 0 0 0 0)
("MRDL" 0.3618 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "I2[20]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x22" "I2[20]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "I2[20]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "I1[19]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x22" "I1[19]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "I1[19]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x22" "O1[4]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x22" "O1[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "I2[13]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x22" "I2[13]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "I2[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "A1[4]" '(0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x22" "A1[4]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "A1[4]" '(
("M1" 0.021 0.97657 0 0 0.97657 0 0)
("M2" 0.021 0.1516 46.5003 0 0.1516 0 0)
("M3" 0.021 0.1516 53.7158 0 0.1516 0 0)
("M4" 0.021 0.1516 60.9308 0 0.1516 0 0)
("M5" 0.021 0.1516 68.1454 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "A1[0]" '(0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x22" "A1[0]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "A1[0]" '(
("M1" 0 0.7856 0 0 0.7856 0 0)
("M2" 0.0366 0.25354 1.10564 0 0.25354 0 0)
("M3" 0.0366 0.1516 8.03243 0 0.1516 0 0)
("M4" 0.0366 0.1516 12.1737 0 0.1516 0 0)
("M5" 0.0366 0.1516 16.3147 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "A1[1]" '(0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x22" "A1[1]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "A1[1]" '(
("M1" 0 0.78725 0 0 0.78725 0 0)
("M2" 0.0366 0.25233 1.10564 0 0.25233 0 0)
("M3" 0.0366 0.1516 7.99937 0 0.1516 0 0)
("M4" 0.0366 0.1516 12.1407 0 0.1516 0 0)
("M5" 0.0366 0.1516 16.2817 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "VSS" '(0 0 0 0 5.49 5.49 5.49 5.49 5.49 5.49)
defineDiodeProtection "SRAM2RW32x22" "VSS" '(0 0 0 0 148.5685 148.5685 148.5685 148.5685 148.5685 148.5685)
defineHierAntennaProp "SRAM2RW32x22" "VSS" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 5.49 2192.49 86.3143 0 2192.49 0 0)
("M6" 5.49 0 0 0 0 0 0)
("M7" 5.49 0 0 0 0 0 0)
("M8" 5.49 0 0 0 0 0 0)
("M9" 5.49 0 0 0 0 0 0)
("MRDL" 5.49 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x22" "O1[19]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x22" "O1[19]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x22" "O2[17]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x22" "O2[17]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "I2[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x22" "I2[1]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "I2[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x22" "O2[6]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x22" "O2[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "A1[3]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x22" "A1[3]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "A1[3]" '(
("M1" 0.0366 0.895918 0 0 0.895918 0 0)
("M2" 0.0366 0.1516 24.477 0 0.1516 0 0)
("M3" 0.0366 0.1516 28.6172 0 0.1516 0 0)
("M4" 0.0366 0.1516 32.7571 0 0.1516 0 0)
("M5" 0.0366 0.1516 36.8968 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "CE1" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineDiodeProtection "SRAM2RW32x22" "CE1" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "CE1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0342 0.29968 3.80244 0 0.29968 0 0)
("M5" 0.0342 0.1516 12.5642 0 0.1516 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "CSB1" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x22" "CSB1" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "CSB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0366 0.424789 1.92429 0 0.424789 0 0)
("M5" 0.0366 0.1516 13.5297 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "VDD" '(0 0 0 0 3.0816 3.0816 3.0816 3.0816 3.0816 3.0816)
defineDiodeProtection "SRAM2RW32x22" "VDD" '(0 0 0 0 164.9681 164.9681 164.9681 164.9681 164.9681 164.9681)
defineHierAntennaProp "SRAM2RW32x22" "VDD" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 3.0816 2211.9 29.267 0 2211.9 0 0)
("M6" 3.0816 0 0 0 0 0 0)
("M7" 3.0816 0 0 0 0 0 0)
("M8" 3.0816 0 0 0 0 0 0)
("M9" 3.0816 0 0 0 0 0 0)
("MRDL" 3.0816 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "I2[11]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x22" "I2[11]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "I2[11]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x22" "O1[7]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x22" "O1[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x22" "O1[17]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x22" "O1[17]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "I2[17]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x22" "I2[17]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "I2[17]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "I2[15]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x22" "I2[15]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "I2[15]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x22" "I2[7]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x22" "I2[7]" '(0.6)
defineHierAntennaProp "SRAM2RW32x22" "I2[7]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x22" "O1[12]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x22" "O1[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[38]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW32x50" "I[38]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[46]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[46]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[46]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW32x50" "I[46]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[18]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[18]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[17]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[17]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[17]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW32x50" "I[17]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[16]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[16]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[16]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW32x50" "I[16]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW32x50" "I[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[14]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW32x50" "I[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[14]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[32]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[32]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[32]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW32x50" "I[32]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "I[32]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[8]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[45]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[45]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW32x50" "I[1]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "I[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "CE" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineDiodeProtection "SRAM1RW32x50" "CE" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "CE" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0342 0.30412 3.80243 0 0.30412 0 0)
("M5" 0.0342 0.1516 12.694 0 0.1516 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[36]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[36]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "VSS" '(0 0 0 0 2.745 2.745 2.745 2.745 2.745 2.745)
defineDiodeProtection "SRAM1RW32x50" "VSS" '(0 0 0 0 231.4295 231.4295 231.4295 231.4295 231.4295 231.4295)
defineHierAntennaProp "SRAM1RW32x50" "VSS" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 2.745 2518.14 116.494 0 2518.14 0 0)
("M6" 2.745 0 0 0 0 0 0)
("M7" 2.745 0 0 0 0 0 0)
("M8" 2.745 0 0 0 0 0 0)
("M9" 2.745 0 0 0 0 0 0)
("MRDL" 2.745 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[5]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW32x50" "I[5]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "I[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[23]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW32x50" "I[23]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "I[23]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[23]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[23]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[5]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "OEB" '(0 0.7986 0.7986 0.7986 0.7986 0.7986 0.7986 0.7986 0.7986 0.7986)
defineDiodeProtection "SRAM1RW32x50" "OEB" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "OEB" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.7986 4.36492 0.966023 0 4.36492 0 0)
("M3" 0.7986 0.1516 6.43131 0 0.1516 0 0)
("M4" 0.7986 0.1516 6.62071 0 0.1516 0 0)
("M5" 0.7986 0.1516 6.81009 0 0.1516 0 0)
("M6" 0.7986 0 0 0 0 0 0)
("M7" 0.7986 0 0 0 0 0 0)
("M8" 0.7986 0 0 0 0 0 0)
("M9" 0.7986 0 0 0 0 0 0)
("MRDL" 0.7986 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "WEB" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineDiodeProtection "SRAM1RW32x50" "WEB" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "WEB" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1461 1.57186 1.03833 0 1.57186 0 0)
("M3" 0.1461 0.1516 11.7964 0 0.1516 0 0)
("M4" 0.1461 0.1516 12.8332 0 0.1516 0 0)
("M5" 0.1461 0.1516 13.8699 0 0.1516 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "CSB" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW32x50" "CSB" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "CSB" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0366 0.429229 1.92429 0 0.429229 0 0)
("M5" 0.0366 0.1516 13.651 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "A[3]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW32x50" "A[3]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "A[3]" '(
("M1" 0.0366 0.763018 0 0 0.763018 0 0)
("M2" 0.0366 0.1516 20.8461 0 0.1516 0 0)
("M3" 0.0366 0.1516 24.9865 0 0.1516 0 0)
("M4" 0.0366 0.1516 29.1267 0 0.1516 0 0)
("M5" 0.0366 0.1516 33.2666 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "A[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW32x50" "A[1]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "A[1]" '(
("M1" 0.0366 0.763018 0 0 0.763018 0 0)
("M2" 0.0366 0.1516 20.8461 0 0.1516 0 0)
("M3" 0.0366 0.1516 24.9865 0 0.1516 0 0)
("M4" 0.0366 0.1516 29.1267 0 0.1516 0 0)
("M5" 0.0366 0.1516 33.2666 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "A[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW32x50" "A[0]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "A[0]" '(
("M1" 0.0366 0.763018 0 0 0.763018 0 0)
("M2" 0.0366 0.1516 20.8461 0 0.1516 0 0)
("M3" 0.0366 0.1516 24.9865 0 0.1516 0 0)
("M4" 0.0366 0.1516 29.1267 0 0.1516 0 0)
("M5" 0.0366 0.1516 33.2666 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "A[4]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW32x50" "A[4]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "A[4]" '(
("M1" 0.0366 0.763018 0 0 0.763018 0 0)
("M2" 0.0366 0.1516 20.8461 0 0.1516 0 0)
("M3" 0.0366 0.1516 24.9865 0 0.1516 0 0)
("M4" 0.0366 0.1516 29.1267 0 0.1516 0 0)
("M5" 0.0366 0.1516 33.2666 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "A[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW32x50" "A[2]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "A[2]" '(
("M1" 0.0366 0.763018 0 0 0.763018 0 0)
("M2" 0.0366 0.1516 20.8461 0 0.1516 0 0)
("M3" 0.0366 0.1516 24.9865 0 0.1516 0 0)
("M4" 0.0366 0.1516 29.1267 0 0.1516 0 0)
("M5" 0.0366 0.1516 33.2666 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "VDD" '(0 0 0 0 1.5408 1.5408 1.5408 1.5408 1.5408 1.5408)
defineDiodeProtection "SRAM1RW32x50" "VDD" '(0 0 0 0 230.853 230.853 230.853 230.853 230.853 230.853)
defineHierAntennaProp "SRAM1RW32x50" "VDD" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 1.5408 2492.72 29.1677 0 2492.72 0 0)
("M6" 1.5408 0 0 0 0 0 0)
("M7" 1.5408 0 0 0 0 0 0)
("M8" 1.5408 0 0 0 0 0 0)
("M9" 1.5408 0 0 0 0 0 0)
("MRDL" 1.5408 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[49]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW32x50" "I[49]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "I[49]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[10]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[10]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW32x50" "I[10]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "I[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[22]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[22]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[47]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW32x50" "I[47]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "I[47]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[47]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[47]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[9]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW32x50" "I[9]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "I[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[22]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW32x50" "I[22]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "I[22]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[29]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW32x50" "I[29]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "I[29]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[29]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[29]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[25]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW32x50" "I[25]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "I[25]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[25]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[25]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[9]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[15]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[35]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW32x50" "I[35]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "I[35]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[35]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[35]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[15]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW32x50" "I[15]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "I[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[44]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW32x50" "I[44]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "I[44]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[45]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW32x50" "I[45]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "I[45]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[26]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[26]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[48]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW32x50" "I[48]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "I[48]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[26]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW32x50" "I[26]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "I[26]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[39]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[39]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[28]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW32x50" "I[28]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "I[28]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[37]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[37]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[12]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[34]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[34]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[34]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW32x50" "I[34]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "I[34]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[11]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[11]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW32x50" "I[11]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "I[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[12]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW32x50" "I[12]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "I[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW32x50" "I[0]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "I[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[49]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[49]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[33]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW32x50" "I[33]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "I[33]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[44]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[44]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[37]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW32x50" "I[37]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "I[37]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[33]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[33]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[4]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[40]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[40]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[24]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW32x50" "I[24]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "I[24]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[4]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW32x50" "I[4]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "I[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[19]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[19]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[48]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[48]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW32x50" "I[2]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "I[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[19]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW32x50" "I[19]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "I[19]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[39]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW32x50" "I[39]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "I[39]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[13]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[13]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW32x50" "I[13]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "I[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[28]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[28]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[27]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW32x50" "I[27]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "I[27]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[21]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[21]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[27]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[27]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[21]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW32x50" "I[21]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "I[21]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[20]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW32x50" "I[20]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "I[20]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[43]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[43]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[43]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW32x50" "I[43]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "I[43]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[8]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW32x50" "I[8]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "I[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[20]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[20]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[31]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[31]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[31]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW32x50" "I[31]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "I[31]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[7]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[7]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW32x50" "I[7]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "I[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1514 62.3746 0 0.1514 0 0)
("M5" 0.021 0.1514 69.5795 0 0.1514 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[42]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[42]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[42]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW32x50" "I[42]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "I[42]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[30]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[30]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[30]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW32x50" "I[30]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "I[30]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[6]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[40]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW32x50" "I[40]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "I[40]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[41]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[41]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[41]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW32x50" "I[41]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "I[41]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[6]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW32x50" "I[6]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "I[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[24]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[24]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[18]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW32x50" "I[18]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "I[18]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW32x50" "I[36]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW32x50" "I[36]" '(0.6)
defineHierAntennaProp "SRAM1RW32x50" "I[36]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW32x50" "O[38]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW32x50" "O[38]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x8" "CE" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineHierAntennaProp "SRAM1RW64x8" "CE" '(
("M1" 0 0.1504 0 0 0.1504 0 0)
("M2" 0 0.1504 0 0 0.1504 0 0)
("M3" 0 0.1504 0 0 0.1504 0 0)
("M4" 0.0342 0.29656 3.80243 0 0.29656 0 0)
("M5" 0.0342 0.1504 12.4729 0 0.1504 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x8" "OEB" '(0 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434)
defineHierAntennaProp "SRAM1RW64x8" "OEB" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1434 0.91756 0.966015 0 0.91756 0 0)
("M3" 0.1434 0.1516 7.36414 0 0.1516 0 0)
("M4" 0.1434 0.1516 8.42076 0 0.1516 0 0)
("M5" 0.1434 0.1516 9.47732 0 0.1516 0 0)
("M6" 0.1434 0 0 0 0 0 0)
("M7" 0.1434 0 0 0 0 0 0)
("M8" 0.1434 0 0 0 0 0 0)
("M9" 0.1434 0 0 0 0 0 0)
("MRDL" 0.1434 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x8" "WEB" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineHierAntennaProp "SRAM1RW64x8" "WEB" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1461 1.56508 1.03833 0 1.56508 0 0)
("M3" 0.1461 0.1516 11.7499 0 0.1516 0 0)
("M4" 0.1461 0.1516 12.7868 0 0.1516 0 0)
("M5" 0.1461 0.1516 13.8235 0 0.1516 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x8" "I[4]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW64x8" "I[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x8" "O[6]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x8" "O[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x8" "I[6]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW64x8" "I[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x8" "O[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x8" "O[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x8" "I[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW64x8" "I[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x8" "O[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x8" "O[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x8" "I[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW64x8" "I[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x8" "CSB" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM1RW64x8" "CSB" '(
("M1" 0 0.1504 0 0 0.1504 0 0)
("M2" 0 0.1504 0 0 0.1504 0 0)
("M3" 0 0.1504 0 0 0.1504 0 0)
("M4" 0.0366 0.419029 1.93575 0 0.419029 0 0)
("M5" 0.0366 0.1504 13.3837 0 0.1504 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x8" "O[7]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x8" "O[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x8" "I[5]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW64x8" "I[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x8" "O[5]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x8" "O[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x8" "I[7]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x8" "I[7]" '(0.6)
defineHierAntennaProp "SRAM1RW64x8" "I[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x8" "A[5]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW64x8" "A[5]" '(0.6)
defineHierAntennaProp "SRAM1RW64x8" "A[5]" '(
("M1" 0.0366 0.811398 0 0 0.811398 0 0)
("M2" 0.0366 0.1504 22.1679 0 0.1504 0 0)
("M3" 0.0366 0.1504 26.2754 0 0.1504 0 0)
("M4" 0.0366 0.1504 30.3827 0 0.1504 0 0)
("M5" 0.0366 0.1504 34.4897 0 0.1504 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x8" "A[4]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW64x8" "A[4]" '(0.6)
defineHierAntennaProp "SRAM1RW64x8" "A[4]" '(
("M1" 0.0366 0.811398 0 0 0.811398 0 0)
("M2" 0.0366 0.1504 22.1679 0 0.1504 0 0)
("M3" 0.0366 0.1504 26.2754 0 0.1504 0 0)
("M4" 0.0366 0.1504 30.3827 0 0.1504 0 0)
("M5" 0.0366 0.1504 34.4897 0 0.1504 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x8" "A[3]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW64x8" "A[3]" '(0.6)
defineHierAntennaProp "SRAM1RW64x8" "A[3]" '(
("M1" 0.0366 0.811398 0 0 0.811398 0 0)
("M2" 0.0366 0.1504 22.1679 0 0.1504 0 0)
("M3" 0.0366 0.1504 26.2754 0 0.1504 0 0)
("M4" 0.0366 0.1504 30.3827 0 0.1504 0 0)
("M5" 0.0366 0.1504 34.4897 0 0.1504 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x8" "A[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW64x8" "A[2]" '(0.6)
defineHierAntennaProp "SRAM1RW64x8" "A[2]" '(
("M1" 0.0366 0.811398 0 0 0.811398 0 0)
("M2" 0.0366 0.1504 22.1679 0 0.1504 0 0)
("M3" 0.0366 0.1504 26.2754 0 0.1504 0 0)
("M4" 0.0366 0.1504 30.3827 0 0.1504 0 0)
("M5" 0.0366 0.1504 34.4897 0 0.1504 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x8" "A[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW64x8" "A[0]" '(0.6)
defineHierAntennaProp "SRAM1RW64x8" "A[0]" '(
("M1" 0.0366 0.811348 0 0 0.811348 0 0)
("M2" 0.0366 0.1504 22.1665 0 0.1504 0 0)
("M3" 0.0366 0.1504 26.2741 0 0.1504 0 0)
("M4" 0.0366 0.1504 30.3813 0 0.1504 0 0)
("M5" 0.0366 0.1504 34.4883 0 0.1504 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x8" "A[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW64x8" "A[1]" '(0.6)
defineHierAntennaProp "SRAM1RW64x8" "A[1]" '(
("M1" 0.0366 0.811398 0 0 0.811398 0 0)
("M2" 0.0366 0.1504 22.1679 0 0.1504 0 0)
("M3" 0.0366 0.1504 26.2754 0 0.1504 0 0)
("M4" 0.0366 0.1504 30.3827 0 0.1504 0 0)
("M5" 0.0366 0.1504 34.4897 0 0.1504 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x8" "O[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x8" "O[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x8" "I[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x8" "I[3]" '(0.6)
defineHierAntennaProp "SRAM1RW64x8" "I[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x8" "O[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x8" "O[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x8" "VDD" '(0 0 0 0 1.5408)
defineHierAntennaProp "SRAM1RW64x8" "VDD" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 1.5408 40.2504 917.385 0 40.2504 0 0)
)
defineGateSize "SRAM1RW64x8" "VSS" '(0 0 0 0 2.745 2.745 2.745 2.745 2.745 2.745)
defineDiodeProtection "SRAM1RW64x8" "VSS" '(0 0 0 0 89.04034 89.04034 89.04034 89.04034 89.04034 89.04034)
defineHierAntennaProp "SRAM1RW64x8" "VSS" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 2.745 1449.02 113.43 0 1449.02 0 0)
("M6" 2.745 0 0 0 0 0 0)
("M7" 2.745 0 0 0 0 0 0)
("M8" 2.745 0 0 0 0 0 0)
("M9" 2.745 0 0 0 0 0 0)
("MRDL" 2.745 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x8" "I[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x8" "I[2]" '(0.6)
defineHierAntennaProp "SRAM1RW64x8" "I[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x8" "O[4]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x8" "O[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277608 0 0 0.277608 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x32" "I[10]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW64x32" "I[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.29328 1.24826 0 1.29328 0 0)
("M4" 0.021 0.1516 62.8289 0 0.1516 0 0)
("M5" 0.021 0.1516 70.0433 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x32" "I[4]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW64x32" "I[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.29328 1.24826 0 1.29328 0 0)
("M4" 0.021 0.1516 62.8289 0 0.1516 0 0)
("M5" 0.021 0.1516 70.0433 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x32" "I[5]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW64x32" "I[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.29328 1.24826 0 1.29328 0 0)
("M4" 0.021 0.1516 62.8289 0 0.1516 0 0)
("M5" 0.021 0.1516 70.0433 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x32" "I[29]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW64x32" "I[29]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.29328 1.24826 0 1.29328 0 0)
("M4" 0.021 0.1516 62.8289 0 0.1516 0 0)
("M5" 0.021 0.1516 70.0433 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x32" "I[28]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW64x32" "I[28]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.29334 1.24826 0 1.29334 0 0)
("M4" 0.021 0.1516 62.8317 0 0.1516 0 0)
("M5" 0.021 0.1516 70.0462 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x32" "I[27]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW64x32" "I[27]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.29328 1.24826 0 1.29328 0 0)
("M4" 0.021 0.1516 62.8289 0 0.1516 0 0)
("M5" 0.021 0.1516 70.0433 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x32" "WEB" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineHierAntennaProp "SRAM1RW64x32" "WEB" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1461 1.58398 1.03834 0 1.58398 0 0)
("M3" 0.1461 0.1516 11.8793 0 0.1516 0 0)
("M4" 0.1461 0.1516 12.9161 0 0.1516 0 0)
("M5" 0.1461 0.1516 13.9528 0 0.1516 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x32" "I[19]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW64x32" "I[19]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.29328 1.24826 0 1.29328 0 0)
("M4" 0.021 0.1516 62.8289 0 0.1516 0 0)
("M5" 0.021 0.1516 70.0433 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x32" "I[24]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW64x32" "I[24]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.29328 1.24826 0 1.29328 0 0)
("M4" 0.021 0.1516 62.8289 0 0.1516 0 0)
("M5" 0.021 0.1516 70.0433 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x32" "I[18]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW64x32" "I[18]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.29328 1.24826 0 1.29328 0 0)
("M4" 0.021 0.1516 62.8289 0 0.1516 0 0)
("M5" 0.021 0.1516 70.0433 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x32" "O[16]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x32" "O[16]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.281944 0 0 0.281944 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x32" "O[6]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x32" "O[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.281944 0 0 0.281944 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x32" "I[23]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x32" "I[23]" '(0.6)
defineHierAntennaProp "SRAM1RW64x32" "I[23]" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.29328 1.24826 0 1.29328 0 0)
("M4" 0.021 0.1516 62.8289 0 0.1516 0 0)
("M5" 0.021 0.1516 70.0433 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x32" "I[9]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x32" "I[9]" '(0.6)
defineHierAntennaProp "SRAM1RW64x32" "I[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.29328 1.24826 0 1.29328 0 0)
("M4" 0.021 0.1516 62.8289 0 0.1516 0 0)
("M5" 0.021 0.1516 70.0433 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x32" "O[14]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x32" "O[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.281944 0 0 0.281944 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x32" "I[8]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x32" "I[8]" '(0.6)
defineHierAntennaProp "SRAM1RW64x32" "I[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.29328 1.24826 0 1.29328 0 0)
("M4" 0.021 0.1516 62.8289 0 0.1516 0 0)
("M5" 0.021 0.1516 70.0433 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x32" "O[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x32" "O[1]" '(
("M1" 0 0.152 0 0 0.152 0 0)
("M2" 0 0.152 0 0 0.152 0 0)
("M3" 0 0.282404 0 0 0.282404 0 0)
("M4" 0 0.152 0 0 0.152 0 0)
("M5" 0 0.152 0 0 0.152 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x32" "I[26]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x32" "I[26]" '(0.6)
defineHierAntennaProp "SRAM1RW64x32" "I[26]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.29328 1.24826 0 1.29328 0 0)
("M4" 0.021 0.1516 62.8289 0 0.1516 0 0)
("M5" 0.021 0.1516 70.0433 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x32" "O[8]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x32" "O[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.281944 0 0 0.281944 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x32" "I[20]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x32" "I[20]" '(0.6)
defineHierAntennaProp "SRAM1RW64x32" "I[20]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.29328 1.24826 0 1.29328 0 0)
("M4" 0.021 0.1516 62.8289 0 0.1516 0 0)
("M5" 0.021 0.1516 70.0433 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x32" "I[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x32" "I[3]" '(0.6)
defineHierAntennaProp "SRAM1RW64x32" "I[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.29328 1.24826 0 1.29328 0 0)
("M4" 0.021 0.1516 62.8289 0 0.1516 0 0)
("M5" 0.021 0.1516 70.0433 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x32" "I[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x32" "I[2]" '(0.6)
defineHierAntennaProp "SRAM1RW64x32" "I[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.29328 1.24826 0 1.29328 0 0)
("M4" 0.021 0.1516 62.8289 0 0.1516 0 0)
("M5" 0.021 0.1516 70.0433 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x32" "O[12]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x32" "O[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.281944 0 0 0.281944 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x32" "I[11]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x32" "I[11]" '(0.6)
defineHierAntennaProp "SRAM1RW64x32" "I[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.29328 1.24826 0 1.29328 0 0)
("M4" 0.021 0.1516 62.8289 0 0.1516 0 0)
("M5" 0.021 0.1516 70.0433 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x32" "O[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x32" "O[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.281944 0 0 0.281944 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x32" "I[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x32" "I[0]" '(0.6)
defineHierAntennaProp "SRAM1RW64x32" "I[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.29328 1.24826 0 1.29328 0 0)
("M4" 0.021 0.1516 62.8289 0 0.1516 0 0)
("M5" 0.021 0.1516 70.0433 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x32" "I[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x32" "I[1]" '(0.6)
defineHierAntennaProp "SRAM1RW64x32" "I[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.29328 1.24826 0 1.29328 0 0)
("M4" 0.021 0.1516 62.8289 0 0.1516 0 0)
("M5" 0.021 0.1516 70.0433 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x32" "O[11]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x32" "O[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.281944 0 0 0.281944 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x32" "O[15]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x32" "O[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.281944 0 0 0.281944 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x32" "I[12]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x32" "I[12]" '(0.6)
defineHierAntennaProp "SRAM1RW64x32" "I[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.29328 1.24826 0 1.29328 0 0)
("M4" 0.021 0.1516 62.8289 0 0.1516 0 0)
("M5" 0.021 0.1516 70.0433 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x32" "O[29]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x32" "O[29]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.281944 0 0 0.281944 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x32" "O[28]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x32" "O[28]" '(
("M1" 0 0.1536 0 0 0.1536 0 0)
("M2" 0 0.1536 0 0 0.1536 0 0)
("M3" 0 0.283344 0 0 0.283344 0 0)
("M4" 0 0.1536 0 0 0.1536 0 0)
("M5" 0 0.1536 0 0 0.1536 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x32" "O[26]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x32" "O[26]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.281944 0 0 0.281944 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x32" "I[21]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x32" "I[21]" '(0.6)
defineHierAntennaProp "SRAM1RW64x32" "I[21]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.29334 1.24826 0 1.29334 0 0)
("M4" 0.021 0.1516 62.8317 0 0.1516 0 0)
("M5" 0.021 0.1516 70.0462 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x32" "I[17]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x32" "I[17]" '(0.6)
defineHierAntennaProp "SRAM1RW64x32" "I[17]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.29328 1.24826 0 1.29328 0 0)
("M4" 0.021 0.1516 62.8289 0 0.1516 0 0)
("M5" 0.021 0.1516 70.0433 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x32" "O[4]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x32" "O[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.281944 0 0 0.281944 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x32" "I[7]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x32" "I[7]" '(0.6)
defineHierAntennaProp "SRAM1RW64x32" "I[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.29328 1.24826 0 1.29328 0 0)
("M4" 0.021 0.1516 62.8289 0 0.1516 0 0)
("M5" 0.021 0.1516 70.0433 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x32" "O[31]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x32" "O[31]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.281944 0 0 0.281944 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x32" "O[19]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x32" "O[19]" '(
("M1" 0 0.1412 0 0 0.1412 0 0)
("M2" 0 0.1412 0 0 0.1412 0 0)
("M3" 0 0.274724 0 0 0.274724 0 0)
("M4" 0 0.1412 0 0 0.1412 0 0)
("M5" 0 0.1412 0 0 0.1412 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x32" "O[7]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x32" "O[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.281944 0 0 0.281944 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x32" "I[22]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x32" "I[22]" '(0.6)
defineHierAntennaProp "SRAM1RW64x32" "I[22]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.29328 1.24826 0 1.29328 0 0)
("M4" 0.021 0.1516 62.8289 0 0.1516 0 0)
("M5" 0.021 0.1516 70.0433 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x32" "O[30]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x32" "O[30]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.281944 0 0 0.281944 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x32" "O[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x32" "O[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.281944 0 0 0.281944 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x32" "I[13]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x32" "I[13]" '(0.6)
defineHierAntennaProp "SRAM1RW64x32" "I[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.29328 1.24826 0 1.29328 0 0)
("M4" 0.021 0.1516 62.8289 0 0.1516 0 0)
("M5" 0.021 0.1516 70.0433 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x32" "O[13]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x32" "O[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.281944 0 0 0.281944 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x32" "I[6]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x32" "I[6]" '(0.6)
defineHierAntennaProp "SRAM1RW64x32" "I[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.29328 1.24826 0 1.29328 0 0)
("M4" 0.021 0.1516 62.8289 0 0.1516 0 0)
("M5" 0.021 0.1516 70.0433 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x32" "I[25]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x32" "I[25]" '(0.6)
defineHierAntennaProp "SRAM1RW64x32" "I[25]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.29328 1.24826 0 1.29328 0 0)
("M4" 0.021 0.1516 62.8289 0 0.1516 0 0)
("M5" 0.021 0.1516 70.0433 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x32" "A[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW64x32" "A[1]" '(0.6)
defineHierAntennaProp "SRAM1RW64x32" "A[1]" '(
("M1" 0.0366 0.724118 0 0 0.724118 0 0)
("M2" 0.0366 0.1516 19.7833 0 0.1516 0 0)
("M3" 0.0366 0.1516 23.9238 0 0.1516 0 0)
("M4" 0.0366 0.1516 28.0641 0 0.1516 0 0)
("M5" 0.0366 0.1516 32.204 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x32" "I[30]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x32" "I[30]" '(0.6)
defineHierAntennaProp "SRAM1RW64x32" "I[30]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.29328 1.24826 0 1.29328 0 0)
("M4" 0.021 0.1516 62.8289 0 0.1516 0 0)
("M5" 0.021 0.1516 70.0433 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x32" "A[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW64x32" "A[0]" '(0.6)
defineHierAntennaProp "SRAM1RW64x32" "A[0]" '(
("M1" 0.0366 0.724118 0 0 0.724118 0 0)
("M2" 0.0366 0.1516 19.7833 0 0.1516 0 0)
("M3" 0.0366 0.1516 23.9238 0 0.1516 0 0)
("M4" 0.0366 0.1516 28.0641 0 0.1516 0 0)
("M5" 0.0366 0.1516 32.204 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x32" "O[17]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x32" "O[17]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.281944 0 0 0.281944 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x32" "I[31]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x32" "I[31]" '(0.6)
defineHierAntennaProp "SRAM1RW64x32" "I[31]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.29328 1.24826 0 1.29328 0 0)
("M4" 0.021 0.1516 62.8289 0 0.1516 0 0)
("M5" 0.021 0.1516 70.0433 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x32" "O[21]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x32" "O[21]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.281944 0 0 0.281944 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x32" "O[20]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x32" "O[20]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.281944 0 0 0.281944 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x32" "O[5]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x32" "O[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.281944 0 0 0.281944 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x32" "O[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x32" "O[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.281944 0 0 0.281944 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x32" "O[27]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x32" "O[27]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.281944 0 0 0.281944 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x32" "O[25]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x32" "O[25]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.281944 0 0 0.281944 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x32" "O[24]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x32" "O[24]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.281944 0 0 0.281944 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x32" "O[23]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x32" "O[23]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.281944 0 0 0.281944 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x32" "O[22]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x32" "O[22]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.281944 0 0 0.281944 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x32" "O[10]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x32" "O[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.281944 0 0 0.281944 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x32" "I[16]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x32" "I[16]" '(0.6)
defineHierAntennaProp "SRAM1RW64x32" "I[16]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.29328 1.24826 0 1.29328 0 0)
("M4" 0.021 0.1516 62.8289 0 0.1516 0 0)
("M5" 0.021 0.1516 70.0433 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x32" "I[15]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x32" "I[15]" '(0.6)
defineHierAntennaProp "SRAM1RW64x32" "I[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.29328 1.24826 0 1.29328 0 0)
("M4" 0.021 0.1516 62.8289 0 0.1516 0 0)
("M5" 0.021 0.1516 70.0433 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x32" "I[14]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x32" "I[14]" '(0.6)
defineHierAntennaProp "SRAM1RW64x32" "I[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.29328 1.24826 0 1.29328 0 0)
("M4" 0.021 0.1516 62.8289 0 0.1516 0 0)
("M5" 0.021 0.1516 70.0433 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x32" "O[9]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x32" "O[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.281944 0 0 0.281944 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x32" "VDD" '(0 0 0 0 1.5408 1.5408 1.5408 1.5408 1.5408 1.5408)
defineDiodeProtection "SRAM1RW64x32" "VDD" '(0 0 0 0 238.4294 238.4294 238.4294 238.4294 238.4294 238.4294)
defineHierAntennaProp "SRAM1RW64x32" "VDD" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 1.5408 2802.92 29.168 0 2802.92 0 0)
("M6" 1.5408 0 0 0 0 0 0)
("M7" 1.5408 0 0 0 0 0 0)
("M8" 1.5408 0 0 0 0 0 0)
("M9" 1.5408 0 0 0 0 0 0)
("MRDL" 1.5408 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x32" "A[4]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW64x32" "A[4]" '(0.6)
defineHierAntennaProp "SRAM1RW64x32" "A[4]" '(
("M1" 0.0366 0.724118 0 0 0.724118 0 0)
("M2" 0.0366 0.1516 19.7833 0 0.1516 0 0)
("M3" 0.0366 0.1516 23.9238 0 0.1516 0 0)
("M4" 0.0366 0.1516 28.0641 0 0.1516 0 0)
("M5" 0.0366 0.1516 32.204 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x32" "A[5]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW64x32" "A[5]" '(0.6)
defineHierAntennaProp "SRAM1RW64x32" "A[5]" '(
("M1" 0.0366 0.724118 0 0 0.724118 0 0)
("M2" 0.0366 0.1516 19.7833 0 0.1516 0 0)
("M3" 0.0366 0.1516 23.9238 0 0.1516 0 0)
("M4" 0.0366 0.1516 28.0641 0 0.1516 0 0)
("M5" 0.0366 0.1516 32.204 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x32" "O[18]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x32" "O[18]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.281944 0 0 0.281944 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x32" "A[3]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW64x32" "A[3]" '(0.6)
defineHierAntennaProp "SRAM1RW64x32" "A[3]" '(
("M1" 0.0366 0.724118 0 0 0.724118 0 0)
("M2" 0.0366 0.1516 19.7833 0 0.1516 0 0)
("M3" 0.0366 0.1516 23.9238 0 0.1516 0 0)
("M4" 0.0366 0.1516 28.0641 0 0.1516 0 0)
("M5" 0.0366 0.1516 32.204 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x32" "CSB" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW64x32" "CSB" '(0.6)
defineHierAntennaProp "SRAM1RW64x32" "CSB" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0366 0.437136 2.06147 0 0.437136 0 0)
("M5" 0.0366 0.1516 14.0042 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x32" "OEB" '(0 0.5178 0.5178 0.5178 0.5178 0.5178 0.5178 0.5178 0.5178 0.5178)
defineDiodeProtection "SRAM1RW64x32" "OEB" '(0.6)
defineHierAntennaProp "SRAM1RW64x32" "OEB" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.5178 2.8927 0.966023 0 2.8927 0 0)
("M3" 0.5178 0.1516 6.55211 0 0.1516 0 0)
("M4" 0.5178 0.1516 6.84444 0 0.1516 0 0)
("M5" 0.5178 0.1516 7.13674 0 0.1516 0 0)
("M6" 0.5178 0 0 0 0 0 0)
("M7" 0.5178 0 0 0 0 0 0)
("M8" 0.5178 0 0 0 0 0 0)
("M9" 0.5178 0 0 0 0 0 0)
("MRDL" 0.5178 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x32" "A[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW64x32" "A[2]" '(0.6)
defineHierAntennaProp "SRAM1RW64x32" "A[2]" '(
("M1" 0.0366 0.724118 0 0 0.724118 0 0)
("M2" 0.0366 0.1516 19.7833 0 0.1516 0 0)
("M3" 0.0366 0.1516 23.9238 0 0.1516 0 0)
("M4" 0.0366 0.1516 28.0641 0 0.1516 0 0)
("M5" 0.0366 0.1516 32.204 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x32" "CE" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineDiodeProtection "SRAM1RW64x32" "CE" '(0.6)
defineHierAntennaProp "SRAM1RW64x32" "CE" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0342 0.30178 4.1566 0 0.30178 0 0)
("M5" 0.0342 0.1516 12.9797 0 0.1516 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x32" "VSS" '(0 0 0 0 2.745 2.745 2.745 2.745 2.745 2.745)
defineDiodeProtection "SRAM1RW64x32" "VSS" '(0 0 0 0 259.9021 259.9021 259.9021 259.9021 259.9021 259.9021)
defineHierAntennaProp "SRAM1RW64x32" "VSS" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 2.745 2841.84 116.943 0 2841.84 0 0)
("M6" 2.745 0 0 0 0 0 0)
("M7" 2.745 0 0 0 0 0 0)
("M8" 2.745 0 0 0 0 0 0)
("M9" 2.745 0 0 0 0 0 0)
("MRDL" 2.745 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x34" "I[12]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW64x34" "I[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x34" "VDD" '(0 0 0 0 1.5408 1.5408 1.5408 1.5408 1.5408 1.5408)
defineDiodeProtection "SRAM1RW64x34" "VDD" '(0 0 0 0 250.3725 250.3725 250.3725 250.3725 250.3725 250.3725)
defineHierAntennaProp "SRAM1RW64x34" "VDD" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 1.5408 2911.32 29.1683 0 2911.32 0 0)
("M6" 1.5408 0 0 0 0 0 0)
("M7" 1.5408 0 0 0 0 0 0)
("M8" 1.5408 0 0 0 0 0 0)
("M9" 1.5408 0 0 0 0 0 0)
("MRDL" 1.5408 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x34" "O[6]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x34" "O[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271084 0 0 0.271084 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x34" "O[20]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x34" "O[20]" '(
("M1" 0 0.1538 0 0 0.1538 0 0)
("M2" 0 0.1538 0 0 0.1538 0 0)
("M3" 0 0.272984 0 0 0.272984 0 0)
("M4" 0 0.1538 0 0 0.1538 0 0)
("M5" 0 0.1538 0 0 0.1538 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x34" "O[5]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x34" "O[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271264 0 0 0.271264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x34" "O[4]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x34" "O[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271084 0 0 0.271084 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x34" "O[26]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x34" "O[26]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271144 0 0 0.271144 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x34" "O[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x34" "O[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271084 0 0 0.271084 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x34" "O[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x34" "O[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271084 0 0 0.271084 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x34" "O[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x34" "O[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271144 0 0 0.271144 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x34" "O[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x34" "O[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271264 0 0 0.271264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x34" "O[27]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x34" "O[27]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271084 0 0 0.271084 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x34" "O[28]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x34" "O[28]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271444 0 0 0.271444 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x34" "O[29]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x34" "O[29]" '(
("M1" 0 0.1536 0 0 0.1536 0 0)
("M2" 0 0.1536 0 0 0.1536 0 0)
("M3" 0 0.272304 0 0 0.272304 0 0)
("M4" 0 0.1536 0 0 0.1536 0 0)
("M5" 0 0.1536 0 0 0.1536 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x34" "A[5]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW64x34" "A[5]" '(0.6)
defineHierAntennaProp "SRAM1RW64x34" "A[5]" '(
("M1" 0.0366 0.823928 0 0 0.823928 0 0)
("M2" 0.0366 0.1516 22.5102 0 0.1516 0 0)
("M3" 0.0366 0.1516 26.6505 0 0.1516 0 0)
("M4" 0.0366 0.1516 30.7906 0 0.1516 0 0)
("M5" 0.0366 0.1516 34.9304 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x34" "O[8]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x34" "O[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271144 0 0 0.271144 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x34" "O[30]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x34" "O[30]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271144 0 0 0.271144 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x34" "O[33]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x34" "O[33]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271144 0 0 0.271144 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x34" "O[10]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x34" "O[10]" '(
("M1" 0 0.1536 0 0 0.1536 0 0)
("M2" 0 0.1536 0 0 0.1536 0 0)
("M3" 0 0.272544 0 0 0.272544 0 0)
("M4" 0 0.1536 0 0 0.1536 0 0)
("M5" 0 0.1536 0 0 0.1536 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x34" "O[11]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x34" "O[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271144 0 0 0.271144 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x34" "O[12]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x34" "O[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271444 0 0 0.271444 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x34" "O[24]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x34" "O[24]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271144 0 0 0.271144 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x34" "O[13]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x34" "O[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.270724 0 0 0.270724 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x34" "O[14]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x34" "O[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271144 0 0 0.271144 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x34" "O[15]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x34" "O[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271144 0 0 0.271144 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x34" "O[16]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x34" "O[16]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271144 0 0 0.271144 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x34" "O[17]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x34" "O[17]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271144 0 0 0.271144 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x34" "O[7]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x34" "O[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271024 0 0 0.271024 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x34" "O[21]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x34" "O[21]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271144 0 0 0.271144 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x34" "I[33]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x34" "I[33]" '(0.6)
defineHierAntennaProp "SRAM1RW64x34" "I[33]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x34" "O[22]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x34" "O[22]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271084 0 0 0.271084 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x34" "O[23]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x34" "O[23]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271144 0 0 0.271144 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x34" "O[18]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x34" "O[18]" '(
("M1" 0 0.1536 0 0 0.1536 0 0)
("M2" 0 0.1536 0 0 0.1536 0 0)
("M3" 0 0.272424 0 0 0.272424 0 0)
("M4" 0 0.1536 0 0 0.1536 0 0)
("M5" 0 0.1536 0 0 0.1536 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x34" "O[9]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x34" "O[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271324 0 0 0.271324 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x34" "O[25]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x34" "O[25]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271084 0 0 0.271084 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x34" "I[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x34" "I[2]" '(0.6)
defineHierAntennaProp "SRAM1RW64x34" "I[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x34" "I[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x34" "I[1]" '(0.6)
defineHierAntennaProp "SRAM1RW64x34" "I[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x34" "I[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x34" "I[0]" '(0.6)
defineHierAntennaProp "SRAM1RW64x34" "I[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x34" "I[27]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x34" "I[27]" '(0.6)
defineHierAntennaProp "SRAM1RW64x34" "I[27]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x34" "I[29]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x34" "I[29]" '(0.6)
defineHierAntennaProp "SRAM1RW64x34" "I[29]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.2817 1.24827 0 1.2817 0 0)
("M4" 0.021 0.1516 62.2775 0 0.1516 0 0)
("M5" 0.021 0.1516 69.492 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x34" "I[28]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x34" "I[28]" '(0.6)
defineHierAntennaProp "SRAM1RW64x34" "I[28]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x34" "I[19]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x34" "I[19]" '(0.6)
defineHierAntennaProp "SRAM1RW64x34" "I[19]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x34" "O[19]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x34" "O[19]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.270828 0 0 0.270828 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x34" "A[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW64x34" "A[0]" '(0.6)
defineHierAntennaProp "SRAM1RW64x34" "A[0]" '(
("M1" 0.0366 0.823928 0 0 0.823928 0 0)
("M2" 0.0366 0.1516 22.5102 0 0.1516 0 0)
("M3" 0.0366 0.1516 26.6505 0 0.1516 0 0)
("M4" 0.0366 0.1516 30.7906 0 0.1516 0 0)
("M5" 0.0366 0.1516 34.9304 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x34" "A[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW64x34" "A[1]" '(0.6)
defineHierAntennaProp "SRAM1RW64x34" "A[1]" '(
("M1" 0.0366 0.823928 0 0 0.823928 0 0)
("M2" 0.0366 0.1516 22.5102 0 0.1516 0 0)
("M3" 0.0366 0.1516 26.6505 0 0.1516 0 0)
("M4" 0.0366 0.1516 30.7906 0 0.1516 0 0)
("M5" 0.0366 0.1516 34.9304 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x34" "A[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW64x34" "A[2]" '(0.6)
defineHierAntennaProp "SRAM1RW64x34" "A[2]" '(
("M1" 0.0366 0.823928 0 0 0.823928 0 0)
("M2" 0.0366 0.1516 22.5102 0 0.1516 0 0)
("M3" 0.0366 0.1516 26.6505 0 0.1516 0 0)
("M4" 0.0366 0.1516 30.7906 0 0.1516 0 0)
("M5" 0.0366 0.1516 34.9304 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x34" "A[3]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW64x34" "A[3]" '(0.6)
defineHierAntennaProp "SRAM1RW64x34" "A[3]" '(
("M1" 0.0366 0.823948 0 0 0.823948 0 0)
("M2" 0.0366 0.1516 22.5108 0 0.1516 0 0)
("M3" 0.0366 0.1516 26.6511 0 0.1516 0 0)
("M4" 0.0366 0.1516 30.7911 0 0.1516 0 0)
("M5" 0.0366 0.1516 34.9309 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x34" "A[4]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW64x34" "A[4]" '(0.6)
defineHierAntennaProp "SRAM1RW64x34" "A[4]" '(
("M1" 0.0366 0.823928 0 0 0.823928 0 0)
("M2" 0.0366 0.1516 22.5102 0 0.1516 0 0)
("M3" 0.0366 0.1516 26.6505 0 0.1516 0 0)
("M4" 0.0366 0.1516 30.7906 0 0.1516 0 0)
("M5" 0.0366 0.1516 34.9304 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x34" "I[18]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x34" "I[18]" '(0.6)
defineHierAntennaProp "SRAM1RW64x34" "I[18]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28152 1.24827 0 1.28152 0 0)
("M4" 0.021 0.1516 62.2689 0 0.1516 0 0)
("M5" 0.021 0.1516 69.4834 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x34" "CE" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineDiodeProtection "SRAM1RW64x34" "CE" '(0.6)
defineHierAntennaProp "SRAM1RW64x34" "CE" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0342 0.281736 3.70059 0 0.281736 0 0)
("M5" 0.0342 0.1516 11.9377 0 0.1516 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x34" "CSB" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW64x34" "CSB" '(0.6)
defineHierAntennaProp "SRAM1RW64x34" "CSB" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0366 0.428652 1.70076 0 0.428652 0 0)
("M5" 0.0366 0.1516 13.4117 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x34" "O[31]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x34" "O[31]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271564 0 0 0.271564 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x34" "O[32]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x34" "O[32]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271144 0 0 0.271144 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x34" "OEB" '(0 0.549 0.549 0.549 0.549 0.549 0.549 0.549 0.549 0.549)
defineDiodeProtection "SRAM1RW64x34" "OEB" '(0.6)
defineHierAntennaProp "SRAM1RW64x34" "OEB" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.549 3.00654 0.966023 0 3.00654 0 0)
("M3" 0.549 0.1516 6.44199 0 0.1516 0 0)
("M4" 0.549 0.1516 6.71769 0 0.1516 0 0)
("M5" 0.549 0.1516 6.99336 0 0.1516 0 0)
("M6" 0.549 0 0 0 0 0 0)
("M7" 0.549 0 0 0 0 0 0)
("M8" 0.549 0 0 0 0 0 0)
("M9" 0.549 0 0 0 0 0 0)
("MRDL" 0.549 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x34" "I[14]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x34" "I[14]" '(0.6)
defineHierAntennaProp "SRAM1RW64x34" "I[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x34" "I[15]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x34" "I[15]" '(0.6)
defineHierAntennaProp "SRAM1RW64x34" "I[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x34" "I[16]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x34" "I[16]" '(0.6)
defineHierAntennaProp "SRAM1RW64x34" "I[16]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x34" "I[17]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x34" "I[17]" '(0.6)
defineHierAntennaProp "SRAM1RW64x34" "I[17]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x34" "WEB" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineDiodeProtection "SRAM1RW64x34" "WEB" '(0.6)
defineHierAntennaProp "SRAM1RW64x34" "WEB" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1461 1.57696 1.03834 0 1.57696 0 0)
("M3" 0.1461 0.1516 11.8313 0 0.1516 0 0)
("M4" 0.1461 0.1516 12.8681 0 0.1516 0 0)
("M5" 0.1461 0.1516 13.9048 0 0.1516 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x34" "I[21]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x34" "I[21]" '(0.6)
defineHierAntennaProp "SRAM1RW64x34" "I[21]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x34" "I[7]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x34" "I[7]" '(0.6)
defineHierAntennaProp "SRAM1RW64x34" "I[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x34" "I[22]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x34" "I[22]" '(0.6)
defineHierAntennaProp "SRAM1RW64x34" "I[22]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x34" "I[8]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x34" "I[8]" '(0.6)
defineHierAntennaProp "SRAM1RW64x34" "I[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x34" "I[23]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x34" "I[23]" '(0.6)
defineHierAntennaProp "SRAM1RW64x34" "I[23]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x34" "I[9]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x34" "I[9]" '(0.6)
defineHierAntennaProp "SRAM1RW64x34" "I[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x34" "I[25]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x34" "I[25]" '(0.6)
defineHierAntennaProp "SRAM1RW64x34" "I[25]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x34" "I[6]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x34" "I[6]" '(0.6)
defineHierAntennaProp "SRAM1RW64x34" "I[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x34" "I[20]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x34" "I[20]" '(0.6)
defineHierAntennaProp "SRAM1RW64x34" "I[20]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x34" "I[5]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x34" "I[5]" '(0.6)
defineHierAntennaProp "SRAM1RW64x34" "I[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x34" "I[26]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x34" "I[26]" '(0.6)
defineHierAntennaProp "SRAM1RW64x34" "I[26]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x34" "I[4]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x34" "I[4]" '(0.6)
defineHierAntennaProp "SRAM1RW64x34" "I[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x34" "I[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x34" "I[3]" '(0.6)
defineHierAntennaProp "SRAM1RW64x34" "I[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x34" "VSS" '(0 0 0 0 2.745 2.745 2.745 2.745 2.745 2.745)
defineDiodeProtection "SRAM1RW64x34" "VSS" '(0 0 0 0 274.1405 274.1405 274.1405 274.1405 274.1405 274.1405)
defineHierAntennaProp "SRAM1RW64x34" "VSS" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 2.745 2873.04 111.853 0 2873.04 0 0)
("M6" 2.745 0 0 0 0 0 0)
("M7" 2.745 0 0 0 0 0 0)
("M8" 2.745 0 0 0 0 0 0)
("M9" 2.745 0 0 0 0 0 0)
("MRDL" 2.745 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x34" "I[10]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x34" "I[10]" '(0.6)
defineHierAntennaProp "SRAM1RW64x34" "I[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x34" "I[30]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x34" "I[30]" '(0.6)
defineHierAntennaProp "SRAM1RW64x34" "I[30]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x34" "I[24]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x34" "I[24]" '(0.6)
defineHierAntennaProp "SRAM1RW64x34" "I[24]" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28297 1.24827 0 1.28297 0 0)
("M4" 0.021 0.1516 62.3381 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5525 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x34" "I[31]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x34" "I[31]" '(0.6)
defineHierAntennaProp "SRAM1RW64x34" "I[31]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x34" "I[11]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x34" "I[11]" '(0.6)
defineHierAntennaProp "SRAM1RW64x34" "I[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28152 1.24827 0 1.28152 0 0)
("M4" 0.021 0.1516 62.2689 0 0.1516 0 0)
("M5" 0.021 0.1516 69.4834 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x34" "I[32]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x34" "I[32]" '(0.6)
defineHierAntennaProp "SRAM1RW64x34" "I[32]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x34" "I[13]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x34" "I[13]" '(0.6)
defineHierAntennaProp "SRAM1RW64x34" "I[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[113]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW64x128" "I[113]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[113]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[113]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[114]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW64x128" "I[114]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[114]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[114]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[115]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW64x128" "I[115]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[116]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[116]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[115]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[115]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[116]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW64x128" "I[116]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[117]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW64x128" "I[117]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[117]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[117]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[118]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[118]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[118]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[118]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[118]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[119]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[119]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[119]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[119]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[119]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[120]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[120]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[120]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[101]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[101]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[102]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[102]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[102]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[102]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[102]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[103]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[103]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[103]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[103]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[103]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[104]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[104]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[104]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[104]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[104]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[105]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[105]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[105]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[105]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[105]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[106]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[106]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[106]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[106]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[106]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[107]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[107]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[107]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[107]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[107]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[108]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[108]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[108]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[108]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[108]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[109]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[109]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[109]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[109]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[109]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[110]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[110]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[110]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[110]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[110]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[65]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[65]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[65]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[65]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[65]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[66]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[66]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[66]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[66]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[66]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[67]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[67]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[67]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[67]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[67]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[68]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[68]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[68]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[68]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[68]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[69]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[69]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[69]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[69]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[69]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[70]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[70]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[70]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[70]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[70]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[71]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[71]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[71]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[71]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[71]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[72]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[72]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[72]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[72]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[72]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[73]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[73]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[73]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[73]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[73]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[74]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[74]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[74]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[56]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[56]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[56]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[56]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[56]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[57]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[57]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[57]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[57]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[57]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[58]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[58]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[58]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[58]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[58]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[60]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[60]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[60]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[60]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[60]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[59]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[59]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[59]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[59]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[59]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[61]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[61]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[61]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[61]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[61]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[62]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[62]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[62]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[62]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[62]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[63]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[63]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[63]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[63]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[63]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[64]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[64]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[64]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[64]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[64]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "CSB" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW64x128" "CSB" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "CSB" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0366 0.426409 1.92429 0 0.426409 0 0)
("M5" 0.0366 0.1516 13.5739 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[46]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[46]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[47]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[47]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[47]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1514 62.3746 0 0.1514 0 0)
("M5" 0.021 0.1514 69.5795 0 0.1514 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[47]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[47]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "CE" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineDiodeProtection "SRAM1RW64x128" "CE" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "CE" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0342 0.3013 3.80244 0 0.3013 0 0)
("M5" 0.0342 0.1516 12.6115 0 0.1516 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[48]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[48]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[49]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[49]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[49]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[49]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[49]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[50]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[50]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[50]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[50]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[50]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[51]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[51]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[51]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[51]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[51]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[52]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[52]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[52]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[52]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[52]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[53]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[53]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[53]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[53]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[53]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[54]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[54]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[54]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[54]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[54]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[55]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[55]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[55]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[55]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[55]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[120]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[120]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[121]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[121]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[121]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[121]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[121]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[122]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[122]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[122]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[122]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[122]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[123]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[123]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[123]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[123]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[123]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[124]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[124]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[124]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[124]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[124]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[125]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[125]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[125]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[125]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[125]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[126]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[126]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[126]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[126]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[126]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[127]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[127]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[127]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[127]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[127]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "OEB" '(0 2.0154 2.0154 2.0154 2.0154 2.0154 2.0154 2.0154 2.0154 2.0154)
defineDiodeProtection "SRAM1RW64x128" "OEB" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "OEB" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 2.0154 10.7672 0.966025 0 10.7672 0 0)
("M3" 2.0154 0.1516 6.30805 0 0.1516 0 0)
("M4" 2.0154 0.1516 6.38285 0 0.1516 0 0)
("M5" 2.0154 0.1516 6.45765 0 0.1516 0 0)
("M6" 2.0154 0 0 0 0 0 0)
("M7" 2.0154 0 0 0 0 0 0)
("M8" 2.0154 0 0 0 0 0 0)
("M9" 2.0154 0 0 0 0 0 0)
("MRDL" 2.0154 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "WEB" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineDiodeProtection "SRAM1RW64x128" "WEB" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "WEB" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1461 1.56898 1.03834 0 1.56898 0 0)
("M3" 0.1461 0.1516 11.7766 0 0.1516 0 0)
("M4" 0.1461 0.1516 12.8134 0 0.1516 0 0)
("M5" 0.1461 0.1516 13.8502 0 0.1516 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[111]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[111]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[111]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[111]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[111]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[112]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[112]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[112]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[112]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[112]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[42]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[42]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[44]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[44]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[41]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[41]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[41]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[41]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[41]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[40]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[40]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[40]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[40]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[40]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[42]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[42]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[42]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[38]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[38]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[38]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[39]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[39]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[37]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[37]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[39]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[39]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[39]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[38]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[38]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[37]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[37]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[37]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[36]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[36]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "A[5]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW64x128" "A[5]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "A[5]" '(
("M1" 0.0366 0.711668 0 0 0.711668 0 0)
("M2" 0.0366 0.1516 19.4432 0 0.1516 0 0)
("M3" 0.0366 0.1516 23.5837 0 0.1516 0 0)
("M4" 0.0366 0.1516 27.724 0 0.1516 0 0)
("M5" 0.0366 0.1516 31.8639 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[2]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[45]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[45]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "VSS" '(0 0 0 0 2.745 2.745 2.745 2.745 2.745 2.745)
defineDiodeProtection "SRAM1RW64x128" "VSS" '(0 0 0 0 943.3489 943.3489 943.3489 943.3489 943.3489 943.3489)
defineHierAntennaProp "SRAM1RW64x128" "VSS" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 2.745 8440 112.164 0 8440 0 0)
("M6" 2.745 0 0 0 0 0 0)
("M7" 2.745 0 0 0 0 0 0)
("M8" 2.745 0 0 0 0 0 0)
("M9" 2.745 0 0 0 0 0 0)
("MRDL" 2.745 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "A[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW64x128" "A[1]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "A[1]" '(
("M1" 0.0366 0.711668 0 0 0.711668 0 0)
("M2" 0.0366 0.1516 19.4432 0 0.1516 0 0)
("M3" 0.0366 0.1516 23.5837 0 0.1516 0 0)
("M4" 0.0366 0.1516 27.724 0 0.1516 0 0)
("M5" 0.0366 0.1516 31.8639 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "A[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW64x128" "A[0]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "A[0]" '(
("M1" 0.0366 0.711668 0 0 0.711668 0 0)
("M2" 0.0366 0.1516 19.4432 0 0.1516 0 0)
("M3" 0.0366 0.1516 23.5837 0 0.1516 0 0)
("M4" 0.0366 0.1516 27.724 0 0.1516 0 0)
("M5" 0.0366 0.1516 31.8639 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "A[4]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW64x128" "A[4]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "A[4]" '(
("M1" 0.0366 0.711668 0 0 0.711668 0 0)
("M2" 0.0366 0.1516 19.4432 0 0.1516 0 0)
("M3" 0.0366 0.1516 23.5837 0 0.1516 0 0)
("M4" 0.0366 0.1516 27.724 0 0.1516 0 0)
("M5" 0.0366 0.1516 31.8639 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "A[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW64x128" "A[2]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "A[2]" '(
("M1" 0.0366 0.711668 0 0 0.711668 0 0)
("M2" 0.0366 0.1516 19.4432 0 0.1516 0 0)
("M3" 0.0366 0.1516 23.5837 0 0.1516 0 0)
("M4" 0.0366 0.1516 27.724 0 0.1516 0 0)
("M5" 0.0366 0.1516 31.8639 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "VDD" '(0 0 0 0 1.5408 1.5408 1.5408 1.5408 1.5408 1.5408)
defineDiodeProtection "SRAM1RW64x128" "VDD" '(0 0 0 0 811.6972 811.6972 811.6972 811.6972 811.6972 811.6972)
defineHierAntennaProp "SRAM1RW64x128" "VDD" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 1.5408 8440.79 29.262 0 8440.79 0 0)
("M6" 1.5408 0 0 0 0 0 0)
("M7" 1.5408 0 0 0 0 0 0)
("M8" 1.5408 0 0 0 0 0 0)
("M9" 1.5408 0 0 0 0 0 0)
("MRDL" 1.5408 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[93]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[93]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[93]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1514 62.3746 0 0.1514 0 0)
("M5" 0.021 0.1514 69.5795 0 0.1514 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[93]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[93]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[98]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[98]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[94]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[94]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[95]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[95]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[95]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[95]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[95]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[96]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[96]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[96]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[96]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[96]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[97]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[97]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[97]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[97]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[97]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[94]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[94]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[94]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[98]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[98]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[98]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[99]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[99]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[99]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[99]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[99]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[100]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[100]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[100]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[100]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[100]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[101]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[101]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[101]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "A[3]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW64x128" "A[3]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "A[3]" '(
("M1" 0.0366 0.711668 0 0 0.711668 0 0)
("M2" 0.0366 0.1516 19.4432 0 0.1516 0 0)
("M3" 0.0366 0.1516 23.5837 0 0.1516 0 0)
("M4" 0.0366 0.1516 27.724 0 0.1516 0 0)
("M5" 0.0366 0.1516 31.8639 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[84]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[84]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[84]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[84]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[84]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[85]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[85]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[85]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[85]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[85]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[86]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[86]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[86]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[86]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[86]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[87]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[87]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[87]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[87]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[87]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[88]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[88]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[88]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[88]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[88]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[89]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[89]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[89]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[89]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[89]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[90]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[90]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[90]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[90]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[90]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[91]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[91]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[91]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[91]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[91]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[92]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[92]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[92]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[92]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[92]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[74]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[74]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[75]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[75]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[75]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[75]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[75]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[76]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[76]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[76]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[76]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[76]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[77]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[77]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[77]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[77]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[77]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[78]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[78]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[78]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[78]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[78]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[79]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[79]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[79]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[79]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[79]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[80]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[80]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[80]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[80]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[80]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[81]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[81]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[81]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[81]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[81]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[82]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[82]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[82]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[82]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[82]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[83]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[83]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[83]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[83]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[83]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[6]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[6]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[6]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[9]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[9]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[8]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[8]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[7]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[4]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[4]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[4]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[3]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[5]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[5]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[5]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[48]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[48]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[48]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[0]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[1]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1514 62.3746 0 0.1514 0 0)
("M5" 0.021 0.1514 69.5795 0 0.1514 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[46]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[46]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[46]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[17]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[17]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[17]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[16]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[16]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[18]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[18]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[18]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[15]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[16]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[16]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[16]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[14]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[14]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[14]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[15]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[15]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[12]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[12]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[12]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[13]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[13]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[13]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[11]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[10]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[9]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[10]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[10]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[11]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[11]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[7]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[7]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[8]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[26]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[26]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[27]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[27]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[27]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[27]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[27]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[25]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[25]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[25]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[24]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[24]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[24]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[24]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[24]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[22]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[22]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[22]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[23]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[23]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[23]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[22]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[22]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[23]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[23]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[18]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[18]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[19]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[19]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[19]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[19]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[19]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[20]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[20]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[20]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[21]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[21]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[21]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[21]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[21]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[20]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[20]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[17]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[17]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[35]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[35]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[36]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[36]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[36]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[34]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[34]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[33]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[33]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[33]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[35]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[35]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[35]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[34]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[34]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[34]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[33]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[33]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[32]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[32]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[32]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[32]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[32]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[31]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[31]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[30]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[30]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[31]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[31]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[31]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[28]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[28]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[28]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[30]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[30]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[30]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[29]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[29]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[28]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[28]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[29]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[29]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[29]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[26]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[26]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[26]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[25]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[25]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[45]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[45]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[45]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[44]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[44]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[44]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW64x128" "O[43]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW64x128" "O[43]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW64x128" "I[43]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW64x128" "I[43]" '(0.6)
defineHierAntennaProp "SRAM1RW64x128" "I[43]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x8" "A[4]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM1RW128x8" "A[4]" '(
("M1" 0.0366 0.727888 0 0 0.727888 0 0)
("M2" 0.0366 0.1504 19.8863 0 0.1504 0 0)
("M3" 0.0366 0.1504 23.994 0 0.1504 0 0)
("M4" 0.0366 0.1504 28.1015 0 0.1504 0 0)
("M5" 0.0366 0.1504 32.2086 0 0.1504 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x8" "A[3]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM1RW128x8" "A[3]" '(
("M1" 0.0366 0.727888 0 0 0.727888 0 0)
("M2" 0.0366 0.1504 19.8863 0 0.1504 0 0)
("M3" 0.0366 0.1504 23.994 0 0.1504 0 0)
("M4" 0.0366 0.1504 28.1015 0 0.1504 0 0)
("M5" 0.0366 0.1504 32.2086 0 0.1504 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x8" "A[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM1RW128x8" "A[2]" '(
("M1" 0.0366 0.727888 0 0 0.727888 0 0)
("M2" 0.0366 0.1504 19.8863 0 0.1504 0 0)
("M3" 0.0366 0.1504 23.994 0 0.1504 0 0)
("M4" 0.0366 0.1504 28.1015 0 0.1504 0 0)
("M5" 0.0366 0.1504 32.2086 0 0.1504 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x8" "A[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM1RW128x8" "A[1]" '(
("M1" 0.0366 0.727888 0 0 0.727888 0 0)
("M2" 0.0366 0.1504 19.8863 0 0.1504 0 0)
("M3" 0.0366 0.1504 23.994 0 0.1504 0 0)
("M4" 0.0366 0.1504 28.1015 0 0.1504 0 0)
("M5" 0.0366 0.1504 32.2086 0 0.1504 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x8" "A[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM1RW128x8" "A[0]" '(
("M1" 0.0366 0.728074 0 0 0.728074 0 0)
("M2" 0.0366 0.1504 19.8914 0 0.1504 0 0)
("M3" 0.0366 0.1504 23.9991 0 0.1504 0 0)
("M4" 0.0366 0.1504 28.1065 0 0.1504 0 0)
("M5" 0.0366 0.1504 32.2137 0 0.1504 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x8" "A[6]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM1RW128x8" "A[6]" '(
("M1" 0.0366 0.727888 0 0 0.727888 0 0)
("M2" 0.0366 0.1504 19.8863 0 0.1504 0 0)
("M3" 0.0366 0.1504 23.994 0 0.1504 0 0)
("M4" 0.0366 0.1504 28.1015 0 0.1504 0 0)
("M5" 0.0366 0.1504 32.2086 0 0.1504 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x8" "OEB" '(0 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434)
defineHierAntennaProp "SRAM1RW128x8" "OEB" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1434 0.91756 0.966015 0 0.91756 0 0)
("M3" 0.1434 0.1516 7.36414 0 0.1516 0 0)
("M4" 0.1434 0.1516 8.42076 0 0.1516 0 0)
("M5" 0.1434 0.1516 9.47732 0 0.1516 0 0)
("M6" 0.1434 0 0 0 0 0 0)
("M7" 0.1434 0 0 0 0 0 0)
("M8" 0.1434 0 0 0 0 0 0)
("M9" 0.1434 0 0 0 0 0 0)
("MRDL" 0.1434 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x8" "WEB" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineHierAntennaProp "SRAM1RW128x8" "WEB" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1461 1.56544 1.03834 0 1.56544 0 0)
("M3" 0.1461 0.1516 11.7524 0 0.1516 0 0)
("M4" 0.1461 0.1516 12.7892 0 0.1516 0 0)
("M5" 0.1461 0.1516 13.8259 0 0.1516 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x8" "I[5]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW128x8" "I[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x8" "I[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW128x8" "I[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x8" "I[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW128x8" "I[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x8" "I[4]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW128x8" "I[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x8" "O[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x8" "O[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x8" "I[6]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW128x8" "I[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x8" "O[6]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x8" "O[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x8" "O[7]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x8" "O[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x8" "I[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x8" "I[0]" '(0.6)
defineHierAntennaProp "SRAM1RW128x8" "I[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x8" "O[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x8" "O[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x8" "I[7]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x8" "I[7]" '(0.6)
defineHierAntennaProp "SRAM1RW128x8" "I[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x8" "CSB" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW128x8" "CSB" '(0.6)
defineHierAntennaProp "SRAM1RW128x8" "CSB" '(
("M1" 0 0.1504 0 0 0.1504 0 0)
("M2" 0 0.1504 0 0 0.1504 0 0)
("M3" 0 0.1504 0 0 0.1504 0 0)
("M4" 0.0366 0.419389 1.93575 0 0.419389 0 0)
("M5" 0.0366 0.1504 13.3936 0 0.1504 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x8" "CE" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineDiodeProtection "SRAM1RW128x8" "CE" '(0.6)
defineHierAntennaProp "SRAM1RW128x8" "CE" '(
("M1" 0 0.1504 0 0 0.1504 0 0)
("M2" 0 0.1504 0 0 0.1504 0 0)
("M3" 0 0.1504 0 0 0.1504 0 0)
("M4" 0.0342 0.29692 3.80243 0 0.29692 0 0)
("M5" 0.0342 0.1504 12.4835 0 0.1504 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x8" "A[5]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW128x8" "A[5]" '(0.6)
defineHierAntennaProp "SRAM1RW128x8" "A[5]" '(
("M1" 0.0366 0.727888 0 0 0.727888 0 0)
("M2" 0.0366 0.1504 19.8863 0 0.1504 0 0)
("M3" 0.0366 0.1504 23.994 0 0.1504 0 0)
("M4" 0.0366 0.1504 28.1015 0 0.1504 0 0)
("M5" 0.0366 0.1504 32.2086 0 0.1504 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x8" "O[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x8" "O[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x8" "I[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x8" "I[2]" '(0.6)
defineHierAntennaProp "SRAM1RW128x8" "I[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x8" "O[5]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x8" "O[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x8" "O[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x8" "O[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x8" "O[4]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x8" "O[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277608 0 0 0.277608 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x8" "VDD" '(0 0 0 0 1.5408 1.5408 1.5408 1.5408 1.5408 1.5408)
defineDiodeProtection "SRAM1RW128x8" "VDD" '(0 0 0 0 149.5915 149.5915 149.5915 149.5915 149.5915 149.5915)
defineHierAntennaProp "SRAM1RW128x8" "VDD" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 1.5408 2479.95 29.1674 0 2479.95 0 0)
("M6" 1.5408 0 0 0 0 0 0)
("M7" 1.5408 0 0 0 0 0 0)
("M8" 1.5408 0 0 0 0 0 0)
("M9" 1.5408 0 0 0 0 0 0)
("MRDL" 1.5408 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x8" "VSS" '(0 0 0 0 2.745 2.745 2.745 2.745 2.745 2.745)
defineDiodeProtection "SRAM1RW128x8" "VSS" '(0 0 0 0 151.3313 151.3313 151.3313 151.3313 151.3313 151.3313)
defineHierAntennaProp "SRAM1RW128x8" "VSS" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 2.745 2479.86 116.943 0 2479.86 0 0)
("M6" 2.745 0 0 0 0 0 0)
("M7" 2.745 0 0 0 0 0 0)
("M8" 2.745 0 0 0 0 0 0)
("M9" 2.745 0 0 0 0 0 0)
("MRDL" 2.745 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x46" "O[8]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x46" "O[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "I[20]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW128x46" "I[20]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x46" "O[43]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x46" "O[43]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "I[43]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW128x46" "I[43]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "I[8]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW128x46" "I[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x46" "O[20]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x46" "O[20]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x46" "O[31]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x46" "O[31]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "A[5]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM1RW128x46" "A[5]" '(
("M1" 0.0366 0.639268 0 0 0.639268 0 0)
("M2" 0.0366 0.1516 17.4652 0 0.1516 0 0)
("M3" 0.0366 0.1516 21.6058 0 0.1516 0 0)
("M4" 0.0366 0.1516 25.7462 0 0.1516 0 0)
("M5" 0.0366 0.1516 29.8863 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "I[16]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW128x46" "I[16]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "A[6]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM1RW128x46" "A[6]" '(
("M1" 0.0366 0.639268 0 0 0.639268 0 0)
("M2" 0.0366 0.1516 17.4652 0 0.1516 0 0)
("M3" 0.0366 0.1516 21.6058 0 0.1516 0 0)
("M4" 0.0366 0.1516 25.7462 0 0.1516 0 0)
("M5" 0.0366 0.1516 29.8863 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "CSB" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM1RW128x46" "CSB" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0366 0.423409 1.92429 0 0.423409 0 0)
("M5" 0.0366 0.1516 13.492 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "WEB" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineHierAntennaProp "SRAM1RW128x46" "WEB" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1461 1.56604 1.03833 0 1.56604 0 0)
("M3" 0.1461 0.1516 11.7565 0 0.1516 0 0)
("M4" 0.1461 0.1516 12.7933 0 0.1516 0 0)
("M5" 0.1461 0.1516 13.8301 0 0.1516 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "I[18]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW128x46" "I[18]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x46" "O[10]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x46" "O[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "CE" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineDiodeProtection "SRAM1RW128x46" "CE" '(0.6)
defineHierAntennaProp "SRAM1RW128x46" "CE" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0342 0.2983 3.80244 0 0.2983 0 0)
("M5" 0.0342 0.1516 12.5238 0 0.1516 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "OEB" '(0 0.7362 0.7362 0.7362 0.7362 0.7362 0.7362 0.7362 0.7362 0.7362)
defineDiodeProtection "SRAM1RW128x46" "OEB" '(0.6)
defineHierAntennaProp "SRAM1RW128x46" "OEB" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.7362 4.05382 0.966024 0 4.05382 0 0)
("M3" 0.7362 0.1516 6.47201 0 0.1516 0 0)
("M4" 0.7362 0.1516 6.67749 0 0.1516 0 0)
("M5" 0.7362 0.1516 6.88296 0 0.1516 0 0)
("M6" 0.7362 0 0 0 0 0 0)
("M7" 0.7362 0 0 0 0 0 0)
("M8" 0.7362 0 0 0 0 0 0)
("M9" 0.7362 0 0 0 0 0 0)
("MRDL" 0.7362 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "VDD" '(0 0 0 0 1.5408 1.5408 1.5408 1.5408 1.5408 1.5408)
defineDiodeProtection "SRAM1RW128x46" "VDD" '(0 0 0 0 534.2204 534.2204 534.2204 534.2204 534.2204 534.2204)
defineHierAntennaProp "SRAM1RW128x46" "VDD" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 1.5408 6404.6 29.1674 0 6404.6 0 0)
("M6" 1.5408 0 0 0 0 0 0)
("M7" 1.5408 0 0 0 0 0 0)
("M8" 1.5408 0 0 0 0 0 0)
("M9" 1.5408 0 0 0 0 0 0)
("MRDL" 1.5408 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x46" "O[33]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x46" "O[33]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x46" "O[15]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x46" "O[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "I[30]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x46" "I[30]" '(0.6)
defineHierAntennaProp "SRAM1RW128x46" "I[30]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "I[15]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x46" "I[15]" '(0.6)
defineHierAntennaProp "SRAM1RW128x46" "I[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "A[3]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW128x46" "A[3]" '(0.6)
defineHierAntennaProp "SRAM1RW128x46" "A[3]" '(
("M1" 0.0366 0.639268 0 0 0.639268 0 0)
("M2" 0.0366 0.1516 17.4652 0 0.1516 0 0)
("M3" 0.0366 0.1516 21.6058 0 0.1516 0 0)
("M4" 0.0366 0.1516 25.7462 0 0.1516 0 0)
("M5" 0.0366 0.1516 29.8863 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "A[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW128x46" "A[1]" '(0.6)
defineHierAntennaProp "SRAM1RW128x46" "A[1]" '(
("M1" 0.0366 0.639268 0 0 0.639268 0 0)
("M2" 0.0366 0.1516 17.4652 0 0.1516 0 0)
("M3" 0.0366 0.1516 21.6058 0 0.1516 0 0)
("M4" 0.0366 0.1516 25.7462 0 0.1516 0 0)
("M5" 0.0366 0.1516 29.8863 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "A[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW128x46" "A[0]" '(0.6)
defineHierAntennaProp "SRAM1RW128x46" "A[0]" '(
("M1" 0.0366 0.639268 0 0 0.639268 0 0)
("M2" 0.0366 0.1516 17.4652 0 0.1516 0 0)
("M3" 0.0366 0.1516 21.6058 0 0.1516 0 0)
("M4" 0.0366 0.1516 25.7462 0 0.1516 0 0)
("M5" 0.0366 0.1516 29.8863 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "A[4]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW128x46" "A[4]" '(0.6)
defineHierAntennaProp "SRAM1RW128x46" "A[4]" '(
("M1" 0.0366 0.639268 0 0 0.639268 0 0)
("M2" 0.0366 0.1516 17.4652 0 0.1516 0 0)
("M3" 0.0366 0.1516 21.6058 0 0.1516 0 0)
("M4" 0.0366 0.1516 25.7462 0 0.1516 0 0)
("M5" 0.0366 0.1516 29.8863 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "A[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW128x46" "A[2]" '(0.6)
defineHierAntennaProp "SRAM1RW128x46" "A[2]" '(
("M1" 0.0366 0.639268 0 0 0.639268 0 0)
("M2" 0.0366 0.1516 17.4652 0 0.1516 0 0)
("M3" 0.0366 0.1516 21.6058 0 0.1516 0 0)
("M4" 0.0366 0.1516 25.7462 0 0.1516 0 0)
("M5" 0.0366 0.1516 29.8863 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "VSS" '(0 0 0 0 2.745 2.745 2.745 2.745 2.745 2.745)
defineDiodeProtection "SRAM1RW128x46" "VSS" '(0 0 0 0 649.0306 649.0306 649.0306 649.0306 649.0306 649.0306)
defineHierAntennaProp "SRAM1RW128x46" "VSS" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 2.745 6473.5 116.942 0 6473.5 0 0)
("M6" 2.745 0 0 0 0 0 0)
("M7" 2.745 0 0 0 0 0 0)
("M8" 2.745 0 0 0 0 0 0)
("M9" 2.745 0 0 0 0 0 0)
("MRDL" 2.745 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x46" "O[42]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x46" "O[42]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x46" "O[45]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x46" "O[45]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "I[37]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x46" "I[37]" '(0.6)
defineHierAntennaProp "SRAM1RW128x46" "I[37]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "I[38]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x46" "I[38]" '(0.6)
defineHierAntennaProp "SRAM1RW128x46" "I[38]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x46" "O[38]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x46" "O[38]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "I[33]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x46" "I[33]" '(0.6)
defineHierAntennaProp "SRAM1RW128x46" "I[33]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x46" "O[21]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x46" "O[21]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "I[12]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x46" "I[12]" '(0.6)
defineHierAntennaProp "SRAM1RW128x46" "I[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x46" "O[12]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x46" "O[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "I[21]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x46" "I[21]" '(0.6)
defineHierAntennaProp "SRAM1RW128x46" "I[21]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "I[9]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x46" "I[9]" '(0.6)
defineHierAntennaProp "SRAM1RW128x46" "I[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "I[24]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x46" "I[24]" '(0.6)
defineHierAntennaProp "SRAM1RW128x46" "I[24]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "I[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x46" "I[0]" '(0.6)
defineHierAntennaProp "SRAM1RW128x46" "I[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x46" "O[24]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x46" "O[24]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "I[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x46" "I[3]" '(0.6)
defineHierAntennaProp "SRAM1RW128x46" "I[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x46" "O[44]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x46" "O[44]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "I[34]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x46" "I[34]" '(0.6)
defineHierAntennaProp "SRAM1RW128x46" "I[34]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x46" "O[37]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x46" "O[37]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "I[45]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x46" "I[45]" '(0.6)
defineHierAntennaProp "SRAM1RW128x46" "I[45]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x46" "O[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x46" "O[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x46" "O[22]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x46" "O[22]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "I[22]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x46" "I[22]" '(0.6)
defineHierAntennaProp "SRAM1RW128x46" "I[22]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "I[29]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x46" "I[29]" '(0.6)
defineHierAntennaProp "SRAM1RW128x46" "I[29]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x46" "O[23]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x46" "O[23]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "I[23]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x46" "I[23]" '(0.6)
defineHierAntennaProp "SRAM1RW128x46" "I[23]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x46" "O[29]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x46" "O[29]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "I[19]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x46" "I[19]" '(0.6)
defineHierAntennaProp "SRAM1RW128x46" "I[19]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x46" "O[19]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x46" "O[19]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "I[42]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x46" "I[42]" '(0.6)
defineHierAntennaProp "SRAM1RW128x46" "I[42]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "I[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x46" "I[1]" '(0.6)
defineHierAntennaProp "SRAM1RW128x46" "I[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "I[44]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x46" "I[44]" '(0.6)
defineHierAntennaProp "SRAM1RW128x46" "I[44]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x46" "O[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x46" "O[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "I[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x46" "I[2]" '(0.6)
defineHierAntennaProp "SRAM1RW128x46" "I[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1514 62.3746 0 0.1514 0 0)
("M5" 0.021 0.1514 69.5795 0 0.1514 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x46" "O[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x46" "O[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x46" "O[35]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x46" "O[35]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x46" "O[13]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x46" "O[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "I[13]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x46" "I[13]" '(0.6)
defineHierAntennaProp "SRAM1RW128x46" "I[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "I[35]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x46" "I[35]" '(0.6)
defineHierAntennaProp "SRAM1RW128x46" "I[35]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "I[27]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x46" "I[27]" '(0.6)
defineHierAntennaProp "SRAM1RW128x46" "I[27]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "I[25]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x46" "I[25]" '(0.6)
defineHierAntennaProp "SRAM1RW128x46" "I[25]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x46" "O[27]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x46" "O[27]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x46" "O[25]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x46" "O[25]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x46" "O[39]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x46" "O[39]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x46" "O[34]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x46" "O[34]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "I[39]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x46" "I[39]" '(0.6)
defineHierAntennaProp "SRAM1RW128x46" "I[39]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x46" "O[36]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x46" "O[36]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "I[36]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x46" "I[36]" '(0.6)
defineHierAntennaProp "SRAM1RW128x46" "I[36]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x46" "O[9]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x46" "O[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "I[31]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x46" "I[31]" '(0.6)
defineHierAntennaProp "SRAM1RW128x46" "I[31]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x46" "O[7]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x46" "O[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "I[7]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x46" "I[7]" '(0.6)
defineHierAntennaProp "SRAM1RW128x46" "I[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x46" "O[28]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x46" "O[28]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "I[26]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x46" "I[26]" '(0.6)
defineHierAntennaProp "SRAM1RW128x46" "I[26]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x46" "O[26]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x46" "O[26]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "I[28]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x46" "I[28]" '(0.6)
defineHierAntennaProp "SRAM1RW128x46" "I[28]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x46" "O[6]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x46" "O[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "I[40]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x46" "I[40]" '(0.6)
defineHierAntennaProp "SRAM1RW128x46" "I[40]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x46" "O[41]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x46" "O[41]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "I[41]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x46" "I[41]" '(0.6)
defineHierAntennaProp "SRAM1RW128x46" "I[41]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "I[6]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x46" "I[6]" '(0.6)
defineHierAntennaProp "SRAM1RW128x46" "I[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x46" "O[5]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x46" "O[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x46" "O[4]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x46" "O[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x46" "O[40]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x46" "O[40]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "I[5]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x46" "I[5]" '(0.6)
defineHierAntennaProp "SRAM1RW128x46" "I[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "I[4]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x46" "I[4]" '(0.6)
defineHierAntennaProp "SRAM1RW128x46" "I[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x46" "O[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x46" "O[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x46" "O[30]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x46" "O[30]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x46" "O[18]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x46" "O[18]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x46" "O[17]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x46" "O[17]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "I[17]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x46" "I[17]" '(0.6)
defineHierAntennaProp "SRAM1RW128x46" "I[17]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x46" "O[16]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x46" "O[16]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "I[10]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x46" "I[10]" '(0.6)
defineHierAntennaProp "SRAM1RW128x46" "I[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x46" "O[11]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x46" "O[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "I[11]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x46" "I[11]" '(0.6)
defineHierAntennaProp "SRAM1RW128x46" "I[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "I[14]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x46" "I[14]" '(0.6)
defineHierAntennaProp "SRAM1RW128x46" "I[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x46" "O[14]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x46" "O[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x46" "O[32]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x46" "O[32]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x46" "I[32]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x46" "I[32]" '(0.6)
defineHierAntennaProp "SRAM1RW128x46" "I[32]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "I[23]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW128x48" "I[23]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x48" "O[5]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x48" "O[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "I[29]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW128x48" "I[29]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x48" "O[4]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x48" "O[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x48" "O[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x48" "O[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "I[33]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW128x48" "I[33]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x48" "O[39]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x48" "O[39]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "I[34]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW128x48" "I[34]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x48" "O[37]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x48" "O[37]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "I[37]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW128x48" "I[37]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "I[22]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW128x48" "I[22]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "A[4]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM1RW128x48" "A[4]" '(
("M1" 0.0366 0.704468 0 0 0.704468 0 0)
("M2" 0.0366 0.1516 19.2465 0 0.1516 0 0)
("M3" 0.0366 0.1516 23.387 0 0.1516 0 0)
("M4" 0.0366 0.1516 27.5273 0 0.1516 0 0)
("M5" 0.0366 0.1516 31.6673 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "A[3]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW128x48" "A[3]" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "A[3]" '(
("M1" 0.0366 0.704468 0 0 0.704468 0 0)
("M2" 0.0366 0.1516 19.2465 0 0.1516 0 0)
("M3" 0.0366 0.1516 23.387 0 0.1516 0 0)
("M4" 0.0366 0.1516 27.5273 0 0.1516 0 0)
("M5" 0.0366 0.1516 31.6673 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "A[5]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW128x48" "A[5]" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "A[5]" '(
("M1" 0.0366 0.704468 0 0 0.704468 0 0)
("M2" 0.0366 0.1516 19.2465 0 0.1516 0 0)
("M3" 0.0366 0.1516 23.387 0 0.1516 0 0)
("M4" 0.0366 0.1516 27.5273 0 0.1516 0 0)
("M5" 0.0366 0.1516 31.6673 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "A[6]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW128x48" "A[6]" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "A[6]" '(
("M1" 0.0366 0.704468 0 0 0.704468 0 0)
("M2" 0.0366 0.1516 19.2465 0 0.1516 0 0)
("M3" 0.0366 0.1516 23.387 0 0.1516 0 0)
("M4" 0.0366 0.1516 27.5273 0 0.1516 0 0)
("M5" 0.0366 0.1516 31.6673 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "CE" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineDiodeProtection "SRAM1RW128x48" "CE" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "CE" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0342 0.37654 3.80246 0 0.37654 0 0)
("M5" 0.0342 0.1516 14.8114 0 0.1516 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "I[47]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x48" "I[47]" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "I[47]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "VSS" '(0 0 0 0 2.745 2.745 2.745 2.745 2.745 2.745)
defineDiodeProtection "SRAM1RW128x48" "VSS" '(0 0 0 0 673.6669 673.6669 673.6669 673.6669 673.6669 673.6669)
defineHierAntennaProp "SRAM1RW128x48" "VSS" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 2.745 6558.56 111.388 0 6558.56 0 0)
("M6" 2.745 0 0 0 0 0 0)
("M7" 2.745 0 0 0 0 0 0)
("M8" 2.745 0 0 0 0 0 0)
("M9" 2.745 0 0 0 0 0 0)
("MRDL" 2.745 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "I[16]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x48" "I[16]" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "I[16]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "I[17]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x48" "I[17]" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "I[17]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "I[18]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x48" "I[18]" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "I[18]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "I[46]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x48" "I[46]" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "I[46]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "I[38]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x48" "I[38]" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "I[38]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "I[36]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x48" "I[36]" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "I[36]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "I[9]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x48" "I[9]" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "I[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "WEB" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineDiodeProtection "SRAM1RW128x48" "WEB" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "WEB" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1461 1.64428 1.03834 0 1.64428 0 0)
("M3" 0.1461 0.1516 12.292 0 0.1516 0 0)
("M4" 0.1461 0.1516 13.3288 0 0.1516 0 0)
("M5" 0.1461 0.1516 14.3655 0 0.1516 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "CSB" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW128x48" "CSB" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "CSB" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0366 0.501649 1.92429 0 0.501649 0 0)
("M5" 0.0366 0.1516 15.6295 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "A[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW128x48" "A[2]" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "A[2]" '(
("M1" 0.0366 0.704468 0 0 0.704468 0 0)
("M2" 0.0366 0.1516 19.2465 0 0.1516 0 0)
("M3" 0.0366 0.1516 23.387 0 0.1516 0 0)
("M4" 0.0366 0.1516 27.5273 0 0.1516 0 0)
("M5" 0.0366 0.1516 31.6673 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "A[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW128x48" "A[1]" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "A[1]" '(
("M1" 0.0366 0.704468 0 0 0.704468 0 0)
("M2" 0.0366 0.1516 19.2465 0 0.1516 0 0)
("M3" 0.0366 0.1516 23.387 0 0.1516 0 0)
("M4" 0.0366 0.1516 27.5273 0 0.1516 0 0)
("M5" 0.0366 0.1516 31.6673 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "A[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW128x48" "A[0]" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "A[0]" '(
("M1" 0.0366 0.704468 0 0 0.704468 0 0)
("M2" 0.0366 0.1516 19.2465 0 0.1516 0 0)
("M3" 0.0366 0.1516 23.387 0 0.1516 0 0)
("M4" 0.0366 0.1516 27.5273 0 0.1516 0 0)
("M5" 0.0366 0.1516 31.6673 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "VDD" '(0 0 0 0 1.5408 1.5408 1.5408 1.5408 1.5408 1.5408)
defineDiodeProtection "SRAM1RW128x48" "VDD" '(0 0 0 0 554.464 554.464 554.464 554.464 554.464 554.464)
defineHierAntennaProp "SRAM1RW128x48" "VDD" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 1.5408 6626.7 29.4852 0 6626.7 0 0)
("M6" 1.5408 0 0 0 0 0 0)
("M7" 1.5408 0 0 0 0 0 0)
("M8" 1.5408 0 0 0 0 0 0)
("M9" 1.5408 0 0 0 0 0 0)
("MRDL" 1.5408 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x48" "O[17]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x48" "O[17]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x48" "O[18]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x48" "O[18]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x48" "O[46]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x48" "O[46]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x48" "O[38]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x48" "O[38]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x48" "O[36]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x48" "O[36]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "I[44]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x48" "I[44]" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "I[44]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "I[39]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x48" "I[39]" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "I[39]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "I[45]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x48" "I[45]" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "I[45]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "I[28]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x48" "I[28]" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "I[28]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "I[35]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x48" "I[35]" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "I[35]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "I[26]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x48" "I[26]" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "I[26]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "I[19]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x48" "I[19]" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "I[19]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "I[27]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x48" "I[27]" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "I[27]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "I[25]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x48" "I[25]" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "I[25]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "I[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x48" "I[3]" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "I[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "I[30]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x48" "I[30]" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "I[30]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x48" "O[9]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x48" "O[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x48" "O[41]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x48" "O[41]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "I[10]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x48" "I[10]" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "I[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x48" "O[10]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x48" "O[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x48" "O[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x48" "O[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x48" "O[40]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x48" "O[40]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "I[41]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x48" "I[41]" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "I[41]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x48" "O[30]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x48" "O[30]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x48" "O[42]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x48" "O[42]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x48" "O[7]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x48" "O[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x48" "O[31]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x48" "O[31]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x48" "O[43]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x48" "O[43]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x48" "O[20]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x48" "O[20]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x48" "O[8]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x48" "O[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x48" "O[32]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x48" "O[32]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x48" "O[14]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x48" "O[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x48" "O[15]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x48" "O[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x48" "O[16]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x48" "O[16]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "I[14]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x48" "I[14]" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "I[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x48" "O[26]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x48" "O[26]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x48" "O[35]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x48" "O[35]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "I[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x48" "I[2]" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "I[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "I[4]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x48" "I[4]" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "I[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x48" "O[19]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x48" "O[19]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "I[12]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x48" "I[12]" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "I[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x48" "O[12]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x48" "O[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "I[11]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x48" "I[11]" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "I[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x48" "O[11]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x48" "O[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "I[7]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x48" "I[7]" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "I[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x48" "O[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x48" "O[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x48" "O[25]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x48" "O[25]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "I[5]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x48" "I[5]" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "I[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "I[13]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x48" "I[13]" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "I[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x48" "O[13]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x48" "O[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "I[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x48" "I[0]" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "I[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x48" "O[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x48" "O[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "I[40]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x48" "I[40]" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "I[40]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x48" "O[22]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x48" "O[22]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x48" "O[34]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x48" "O[34]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "I[15]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x48" "I[15]" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "I[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x48" "O[33]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x48" "O[33]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "I[42]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x48" "I[42]" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "I[42]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x48" "O[29]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x48" "O[29]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "I[32]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x48" "I[32]" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "I[32]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x48" "O[23]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x48" "O[23]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "I[31]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x48" "I[31]" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "I[31]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x48" "O[24]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x48" "O[24]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "I[20]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x48" "I[20]" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "I[20]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "I[43]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x48" "I[43]" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "I[43]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x48" "O[47]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x48" "O[47]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x48" "O[45]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x48" "O[45]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "I[8]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x48" "I[8]" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "I[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x48" "O[27]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x48" "O[27]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "I[6]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x48" "I[6]" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "I[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x48" "O[28]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x48" "O[28]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "I[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x48" "I[1]" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "I[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x48" "O[6]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x48" "O[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x48" "O[44]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x48" "O[44]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW128x48" "O[21]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW128x48" "O[21]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "I[21]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x48" "I[21]" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "I[21]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1514 62.3746 0 0.1514 0 0)
("M5" 0.021 0.1514 69.5795 0 0.1514 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "I[24]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW128x48" "I[24]" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "I[24]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW128x48" "OEB" '(0 0.7674 0.7674 0.7674 0.7674 0.7674 0.7674 0.7674 0.7674 0.7674)
defineDiodeProtection "SRAM1RW128x48" "OEB" '(0.6)
defineHierAntennaProp "SRAM1RW128x48" "OEB" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.7674 4.19638 0.966023 0 4.19638 0 0)
("M3" 0.7674 0.1516 6.43391 0 0.1516 0 0)
("M4" 0.7674 0.1516 6.63102 0 0.1516 0 0)
("M5" 0.7674 0.1516 6.82812 0 0.1516 0 0)
("M6" 0.7674 0 0 0 0 0 0)
("M7" 0.7674 0 0 0 0 0 0)
("M8" 0.7674 0 0 0 0 0 0)
("M9" 0.7674 0 0 0 0 0 0)
("MRDL" 0.7674 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x8" "A[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM1RW256x8" "A[1]" '(
("M1" 0.0366 0.261448 0 0 0.261448 0 0)
("M2" 0.0366 0.1498 7.14291 0 0.1498 0 0)
("M3" 0.0366 0.1498 11.2351 0 0.1498 0 0)
("M4" 0.0366 0.1498 15.3269 0 0.1498 0 0)
("M5" 0.0366 0.1498 19.4185 0 0.1498 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x8" "A[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM1RW256x8" "A[0]" '(
("M1" 0.0366 0.261898 0 0 0.261898 0 0)
("M2" 0.0366 0.1504 7.15521 0 0.1504 0 0)
("M3" 0.0366 0.1504 11.2638 0 0.1504 0 0)
("M4" 0.0366 0.1504 15.372 0 0.1504 0 0)
("M5" 0.0366 0.1504 19.48 0 0.1504 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x8" "OEB" '(0 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434)
defineHierAntennaProp "SRAM1RW256x8" "OEB" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1434 0.91756 0.966015 0 0.91756 0 0)
("M3" 0.1434 0.1516 7.36414 0 0.1516 0 0)
("M4" 0.1434 0.1516 8.42076 0 0.1516 0 0)
("M5" 0.1434 0.1516 9.47732 0 0.1516 0 0)
("M6" 0.1434 0 0 0 0 0 0)
("M7" 0.1434 0 0 0 0 0 0)
("M8" 0.1434 0 0 0 0 0 0)
("M9" 0.1434 0 0 0 0 0 0)
("MRDL" 0.1434 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x8" "CE" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineHierAntennaProp "SRAM1RW256x8" "CE" '(
("M1" 0 0.1498 0 0 0.1498 0 0)
("M2" 0 0.1498 0 0 0.1498 0 0)
("M3" 0 0.1498 0 0 0.1498 0 0)
("M4" 0.0342 0.48718 3.80248 0 0.48718 0 0)
("M5" 0.0342 0.1498 18.0463 0 0.1498 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x8" "WEB" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineHierAntennaProp "SRAM1RW256x8" "WEB" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1461 1.74478 1.03833 0 1.74478 0 0)
("M3" 0.1461 0.1516 12.9798 0 0.1516 0 0)
("M4" 0.1461 0.1516 14.0166 0 0.1516 0 0)
("M5" 0.1461 0.1516 15.0532 0 0.1516 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x8" "A[7]" '(0 0 0 0.1326 0.1326 0.1326 0.1326 0.1326 0.1326 0.1326)
defineHierAntennaProp "SRAM1RW256x8" "A[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.1326 2.30692 26.9555 0 2.30692 0 0)
("M5" 0.1326 0.1516 44.3502 0 0.1516 0 0)
("M6" 0.1326 0 0 0 0 0 0)
("M7" 0.1326 0 0 0 0 0 0)
("M8" 0.1326 0 0 0 0 0 0)
("M9" 0.1326 0 0 0 0 0 0)
("MRDL" 0.1326 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x8" "I[7]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW256x8" "I[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x8" "O[5]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x8" "O[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x8" "O[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x8" "O[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x8" "O[6]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x8" "O[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x8" "I[4]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW256x8" "I[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x8" "I[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW256x8" "I[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x8" "I[6]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW256x8" "I[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x8" "O[4]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x8" "O[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277608 0 0 0.277608 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x8" "O[7]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x8" "O[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x8" "O[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x8" "O[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x8" "I[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x8" "I[0]" '(0.6)
defineHierAntennaProp "SRAM1RW256x8" "I[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x8" "CSB" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW256x8" "CSB" '(0.6)
defineHierAntennaProp "SRAM1RW256x8" "CSB" '(
("M1" 0 0.1498 0 0 0.1498 0 0)
("M2" 0 0.1498 0 0 0.1498 0 0)
("M3" 0 0.1498 0 0 0.1498 0 0)
("M4" 0.0366 0.609889 1.93572 0 0.609889 0 0)
("M5" 0.0366 0.1498 18.5981 0 0.1498 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x8" "A[5]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW256x8" "A[5]" '(0.6)
defineHierAntennaProp "SRAM1RW256x8" "A[5]" '(
("M1" 0.0366 0.261498 0 0 0.261498 0 0)
("M2" 0.0366 0.1498 7.14427 0 0.1498 0 0)
("M3" 0.0366 0.1498 11.2364 0 0.1498 0 0)
("M4" 0.0366 0.1498 15.3283 0 0.1498 0 0)
("M5" 0.0366 0.1498 19.4199 0 0.1498 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x8" "A[6]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW256x8" "A[6]" '(0.6)
defineHierAntennaProp "SRAM1RW256x8" "A[6]" '(
("M1" 0.0366 0.26199 0 0 0.26199 0 0)
("M2" 0.0366 0.1504 7.15772 0 0.1504 0 0)
("M3" 0.0366 0.1504 11.2663 0 0.1504 0 0)
("M4" 0.0366 0.1504 15.3745 0 0.1504 0 0)
("M5" 0.0366 0.1504 19.4825 0 0.1504 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x8" "A[4]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW256x8" "A[4]" '(0.6)
defineHierAntennaProp "SRAM1RW256x8" "A[4]" '(
("M1" 0.0366 0.261448 0 0 0.261448 0 0)
("M2" 0.0366 0.1498 7.14291 0 0.1498 0 0)
("M3" 0.0366 0.1498 11.2351 0 0.1498 0 0)
("M4" 0.0366 0.1498 15.3269 0 0.1498 0 0)
("M5" 0.0366 0.1498 19.4185 0 0.1498 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x8" "A[3]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW256x8" "A[3]" '(0.6)
defineHierAntennaProp "SRAM1RW256x8" "A[3]" '(
("M1" 0.0366 0.261748 0 0 0.261748 0 0)
("M2" 0.0366 0.1502 7.1511 0 0.1502 0 0)
("M3" 0.0366 0.1502 11.2542 0 0.1502 0 0)
("M4" 0.0366 0.1502 15.357 0 0.1502 0 0)
("M5" 0.0366 0.1502 19.4595 0 0.1502 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x8" "A[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW256x8" "A[2]" '(0.6)
defineHierAntennaProp "SRAM1RW256x8" "A[2]" '(
("M1" 0.0366 0.259541 0 0 0.259541 0 0)
("M2" 0.0366 0.1472 7.0908 0 0.1472 0 0)
("M3" 0.0366 0.1472 11.1119 0 0.1472 0 0)
("M4" 0.0366 0.1472 15.1327 0 0.1472 0 0)
("M5" 0.0366 0.1472 19.1533 0 0.1472 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x8" "O[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x8" "O[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x8" "I[5]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x8" "I[5]" '(0.6)
defineHierAntennaProp "SRAM1RW256x8" "I[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x8" "I[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x8" "I[3]" '(0.6)
defineHierAntennaProp "SRAM1RW256x8" "I[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x8" "I[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x8" "I[2]" '(0.6)
defineHierAntennaProp "SRAM1RW256x8" "I[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x8" "O[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x8" "O[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x8" "VDD" '(0 0 0 0 1.5408 1.5408 1.5408 1.5408 1.5408 1.5408)
defineDiodeProtection "SRAM1RW256x8" "VDD" '(0 0 0 0 220.1223 220.1223 220.1223 220.1223 220.1223 220.1223)
defineHierAntennaProp "SRAM1RW256x8" "VDD" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 1.5408 2800.14 29.1677 0 2800.14 0 0)
("M6" 1.5408 0 0 0 0 0 0)
("M7" 1.5408 0 0 0 0 0 0)
("M8" 1.5408 0 0 0 0 0 0)
("M9" 1.5408 0 0 0 0 0 0)
("MRDL" 1.5408 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x8" "VSS" '(0 0 0 0 2.745 2.745 2.745 2.745 2.745 2.745)
defineDiodeProtection "SRAM1RW256x8" "VSS" '(0 0 0 0 250.2488 250.2488 250.2488 250.2488 250.2488 250.2488)
defineHierAntennaProp "SRAM1RW256x8" "VSS" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 2.745 2800.17 115.455 0 2800.17 0 0)
("M6" 2.745 0 0 0 0 0 0)
("M7" 2.745 0 0 0 0 0 0)
("M8" 2.745 0 0 0 0 0 0)
("M9" 2.745 0 0 0 0 0 0)
("MRDL" 2.745 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x32" "I[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW256x32" "I[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27546 1.24826 0 1.27546 0 0)
("M4" 0.021 0.1516 61.9804 0 0.1516 0 0)
("M5" 0.021 0.1516 69.1948 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x32" "O[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x32" "O[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264124 0 0 0.264124 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x32" "O[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x32" "O[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264124 0 0 0.264124 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x32" "I[4]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW256x32" "I[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27546 1.24826 0 1.27546 0 0)
("M4" 0.021 0.1516 61.9804 0 0.1516 0 0)
("M5" 0.021 0.1516 69.1948 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x32" "O[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x32" "O[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264544 0 0 0.264544 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x32" "O[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x32" "O[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264124 0 0 0.264124 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x32" "I[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW256x32" "I[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27546 1.24826 0 1.27546 0 0)
("M4" 0.021 0.1516 61.9804 0 0.1516 0 0)
("M5" 0.021 0.1516 69.1948 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x32" "I[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW256x32" "I[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27546 1.24826 0 1.27546 0 0)
("M4" 0.021 0.1516 61.9804 0 0.1516 0 0)
("M5" 0.021 0.1516 69.1948 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x32" "CE" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineHierAntennaProp "SRAM1RW256x32" "CE" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0342 0.280952 3.70058 0 0.280952 0 0)
("M5" 0.0342 0.1516 11.9148 0 0.1516 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x32" "A[7]" '(0 0 0 0.4206 0.4206 0.4206 0.4206 0.4206 0.4206 0.4206)
defineHierAntennaProp "SRAM1RW256x32" "A[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.4206 6.72683 29.3901 0 6.72683 0 0)
("M5" 0.4206 0.1516 45.3806 0 0.1516 0 0)
("M6" 0.4206 0 0 0 0 0 0)
("M7" 0.4206 0 0 0 0 0 0)
("M8" 0.4206 0 0 0 0 0 0)
("M9" 0.4206 0 0 0 0 0 0)
("MRDL" 0.4206 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x32" "OEB" '(0 0.5178 0.5178 0.5178 0.5178 0.5178 0.5178 0.5178 0.5178 0.5178)
defineHierAntennaProp "SRAM1RW256x32" "OEB" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.5178 2.88046 0.966023 0 2.88046 0 0)
("M3" 0.5178 0.1516 6.52847 0 0.1516 0 0)
("M4" 0.5178 0.1516 6.8208 0 0.1516 0 0)
("M5" 0.5178 0.1516 7.11311 0 0.1516 0 0)
("M6" 0.5178 0 0 0 0 0 0)
("M7" 0.5178 0 0 0 0 0 0)
("M8" 0.5178 0 0 0 0 0 0)
("M9" 0.5178 0 0 0 0 0 0)
("MRDL" 0.5178 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x32" "WEB" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineHierAntennaProp "SRAM1RW256x32" "WEB" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1461 1.5754 1.03833 0 1.5754 0 0)
("M3" 0.1461 0.1516 11.8206 0 0.1516 0 0)
("M4" 0.1461 0.1516 12.8574 0 0.1516 0 0)
("M5" 0.1461 0.1516 13.8941 0 0.1516 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x32" "CSB" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM1RW256x32" "CSB" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0366 0.42714 1.70076 0 0.42714 0 0)
("M5" 0.0366 0.1516 13.3704 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x32" "I[16]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW256x32" "I[16]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27546 1.24826 0 1.27546 0 0)
("M4" 0.021 0.1516 61.9804 0 0.1516 0 0)
("M5" 0.021 0.1516 69.1948 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x32" "I[12]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x32" "I[12]" '(0.6)
defineHierAntennaProp "SRAM1RW256x32" "I[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27546 1.24826 0 1.27546 0 0)
("M4" 0.021 0.1516 61.9804 0 0.1516 0 0)
("M5" 0.021 0.1516 69.1948 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x32" "I[11]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x32" "I[11]" '(0.6)
defineHierAntennaProp "SRAM1RW256x32" "I[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27546 1.24826 0 1.27546 0 0)
("M4" 0.021 0.1516 61.9804 0 0.1516 0 0)
("M5" 0.021 0.1516 69.1948 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x32" "I[10]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x32" "I[10]" '(0.6)
defineHierAntennaProp "SRAM1RW256x32" "I[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27546 1.24826 0 1.27546 0 0)
("M4" 0.021 0.1516 61.9804 0 0.1516 0 0)
("M5" 0.021 0.1516 69.1948 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x32" "I[9]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x32" "I[9]" '(0.6)
defineHierAntennaProp "SRAM1RW256x32" "I[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27546 1.24826 0 1.27546 0 0)
("M4" 0.021 0.1516 61.9804 0 0.1516 0 0)
("M5" 0.021 0.1516 69.1948 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x32" "O[12]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x32" "O[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264124 0 0 0.264124 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x32" "O[11]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x32" "O[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264124 0 0 0.264124 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x32" "O[10]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x32" "O[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264124 0 0 0.264124 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x32" "O[9]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x32" "O[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264124 0 0 0.264124 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x32" "O[7]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x32" "O[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.263704 0 0 0.263704 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x32" "O[6]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x32" "O[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264424 0 0 0.264424 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x32" "I[8]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x32" "I[8]" '(0.6)
defineHierAntennaProp "SRAM1RW256x32" "I[8]" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27648 1.24826 0 1.27648 0 0)
("M4" 0.021 0.1516 62.029 0 0.1516 0 0)
("M5" 0.021 0.1516 69.2435 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x32" "I[7]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x32" "I[7]" '(0.6)
defineHierAntennaProp "SRAM1RW256x32" "I[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27546 1.24826 0 1.27546 0 0)
("M4" 0.021 0.1516 61.9804 0 0.1516 0 0)
("M5" 0.021 0.1516 69.1948 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x32" "O[8]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x32" "O[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264124 0 0 0.264124 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x32" "O[5]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x32" "O[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264124 0 0 0.264124 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x32" "O[4]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x32" "O[4]" '(
("M1" 0 0.1536 0 0 0.1536 0 0)
("M2" 0 0.1536 0 0 0.1536 0 0)
("M3" 0 0.265524 0 0 0.265524 0 0)
("M4" 0 0.1536 0 0 0.1536 0 0)
("M5" 0 0.1536 0 0 0.1536 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x32" "I[5]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x32" "I[5]" '(0.6)
defineHierAntennaProp "SRAM1RW256x32" "I[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.2751 1.24826 0 1.2751 0 0)
("M4" 0.021 0.1516 61.9632 0 0.1516 0 0)
("M5" 0.021 0.1516 69.1777 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x32" "I[6]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x32" "I[6]" '(0.6)
defineHierAntennaProp "SRAM1RW256x32" "I[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27546 1.24826 0 1.27546 0 0)
("M4" 0.021 0.1516 61.9804 0 0.1516 0 0)
("M5" 0.021 0.1516 69.1948 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x32" "I[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x32" "I[3]" '(0.6)
defineHierAntennaProp "SRAM1RW256x32" "I[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27546 1.24826 0 1.27546 0 0)
("M4" 0.021 0.1516 61.9804 0 0.1516 0 0)
("M5" 0.021 0.1516 69.1948 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x32" "O[22]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x32" "O[22]" '(
("M1" 0 0.1538 0 0 0.1538 0 0)
("M2" 0 0.1538 0 0 0.1538 0 0)
("M3" 0 0.265964 0 0 0.265964 0 0)
("M4" 0 0.1538 0 0 0.1538 0 0)
("M5" 0 0.1538 0 0 0.1538 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x32" "I[24]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x32" "I[24]" '(0.6)
defineHierAntennaProp "SRAM1RW256x32" "I[24]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27546 1.24826 0 1.27546 0 0)
("M4" 0.021 0.1516 61.9804 0 0.1516 0 0)
("M5" 0.021 0.1516 69.1948 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x32" "I[23]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x32" "I[23]" '(0.6)
defineHierAntennaProp "SRAM1RW256x32" "I[23]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27546 1.24826 0 1.27546 0 0)
("M4" 0.021 0.1516 61.9804 0 0.1516 0 0)
("M5" 0.021 0.1516 69.1948 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x32" "I[22]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x32" "I[22]" '(0.6)
defineHierAntennaProp "SRAM1RW256x32" "I[22]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27546 1.24826 0 1.27546 0 0)
("M4" 0.021 0.1516 61.9804 0 0.1516 0 0)
("M5" 0.021 0.1516 69.1948 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x32" "O[19]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x32" "O[19]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264304 0 0 0.264304 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x32" "I[20]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x32" "I[20]" '(0.6)
defineHierAntennaProp "SRAM1RW256x32" "I[20]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27546 1.24826 0 1.27546 0 0)
("M4" 0.021 0.1516 61.9804 0 0.1516 0 0)
("M5" 0.021 0.1516 69.1948 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x32" "I[19]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x32" "I[19]" '(0.6)
defineHierAntennaProp "SRAM1RW256x32" "I[19]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27546 1.24826 0 1.27546 0 0)
("M4" 0.021 0.1516 61.9804 0 0.1516 0 0)
("M5" 0.021 0.1516 69.1948 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x32" "O[17]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x32" "O[17]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264124 0 0 0.264124 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x32" "I[18]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x32" "I[18]" '(0.6)
defineHierAntennaProp "SRAM1RW256x32" "I[18]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27546 1.24826 0 1.27546 0 0)
("M4" 0.021 0.1516 61.9804 0 0.1516 0 0)
("M5" 0.021 0.1516 69.1948 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x32" "O[20]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x32" "O[20]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264064 0 0 0.264064 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x32" "I[17]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x32" "I[17]" '(0.6)
defineHierAntennaProp "SRAM1RW256x32" "I[17]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27546 1.24826 0 1.27546 0 0)
("M4" 0.021 0.1516 61.9804 0 0.1516 0 0)
("M5" 0.021 0.1516 69.1948 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x32" "O[18]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x32" "O[18]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264124 0 0 0.264124 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x32" "I[14]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x32" "I[14]" '(0.6)
defineHierAntennaProp "SRAM1RW256x32" "I[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27546 1.24826 0 1.27546 0 0)
("M4" 0.021 0.1516 61.9804 0 0.1516 0 0)
("M5" 0.021 0.1516 69.1948 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x32" "I[13]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x32" "I[13]" '(0.6)
defineHierAntennaProp "SRAM1RW256x32" "I[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.2751 1.24826 0 1.2751 0 0)
("M4" 0.021 0.1516 61.9632 0 0.1516 0 0)
("M5" 0.021 0.1516 69.1777 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x32" "O[14]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x32" "O[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264124 0 0 0.264124 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x32" "O[13]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x32" "O[13]" '(
("M1" 0 0.1536 0 0 0.1536 0 0)
("M2" 0 0.1536 0 0 0.1536 0 0)
("M3" 0 0.265404 0 0 0.265404 0 0)
("M4" 0 0.1536 0 0 0.1536 0 0)
("M5" 0 0.1536 0 0 0.1536 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x32" "I[15]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x32" "I[15]" '(0.6)
defineHierAntennaProp "SRAM1RW256x32" "I[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27546 1.24826 0 1.27546 0 0)
("M4" 0.021 0.1516 61.9804 0 0.1516 0 0)
("M5" 0.021 0.1516 69.1948 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x32" "O[16]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x32" "O[16]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264064 0 0 0.264064 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x32" "O[15]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x32" "O[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264004 0 0 0.264004 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x32" "O[30]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x32" "O[30]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264064 0 0 0.264064 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x32" "O[29]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x32" "O[29]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264244 0 0 0.264244 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x32" "I[30]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x32" "I[30]" '(0.6)
defineHierAntennaProp "SRAM1RW256x32" "I[30]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27546 1.24826 0 1.27546 0 0)
("M4" 0.021 0.1516 61.9804 0 0.1516 0 0)
("M5" 0.021 0.1516 69.1948 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x32" "I[29]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x32" "I[29]" '(0.6)
defineHierAntennaProp "SRAM1RW256x32" "I[29]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27546 1.24826 0 1.27546 0 0)
("M4" 0.021 0.1516 61.9804 0 0.1516 0 0)
("M5" 0.021 0.1516 69.1948 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x32" "I[31]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x32" "I[31]" '(0.6)
defineHierAntennaProp "SRAM1RW256x32" "I[31]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27546 1.24826 0 1.27546 0 0)
("M4" 0.021 0.1516 61.9804 0 0.1516 0 0)
("M5" 0.021 0.1516 69.1948 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x32" "O[31]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x32" "O[31]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264424 0 0 0.264424 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x32" "I[28]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x32" "I[28]" '(0.6)
defineHierAntennaProp "SRAM1RW256x32" "I[28]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27546 1.24826 0 1.27546 0 0)
("M4" 0.021 0.1516 61.9804 0 0.1516 0 0)
("M5" 0.021 0.1516 69.1948 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x32" "I[27]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x32" "I[27]" '(0.6)
defineHierAntennaProp "SRAM1RW256x32" "I[27]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27546 1.24826 0 1.27546 0 0)
("M4" 0.021 0.1516 61.9804 0 0.1516 0 0)
("M5" 0.021 0.1516 69.1948 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x32" "I[26]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x32" "I[26]" '(0.6)
defineHierAntennaProp "SRAM1RW256x32" "I[26]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27546 1.24826 0 1.27546 0 0)
("M4" 0.021 0.1516 61.9804 0 0.1516 0 0)
("M5" 0.021 0.1516 69.1948 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x32" "I[25]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x32" "I[25]" '(0.6)
defineHierAntennaProp "SRAM1RW256x32" "I[25]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27546 1.24826 0 1.27546 0 0)
("M4" 0.021 0.1516 61.9804 0 0.1516 0 0)
("M5" 0.021 0.1516 69.1948 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x32" "O[28]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x32" "O[28]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264124 0 0 0.264124 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x32" "O[27]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x32" "O[27]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264064 0 0 0.264064 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x32" "O[26]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x32" "O[26]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264064 0 0 0.264064 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x32" "O[25]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x32" "O[25]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264064 0 0 0.264064 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x32" "I[21]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x32" "I[21]" '(0.6)
defineHierAntennaProp "SRAM1RW256x32" "I[21]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27546 1.24826 0 1.27546 0 0)
("M4" 0.021 0.1516 61.9804 0 0.1516 0 0)
("M5" 0.021 0.1516 69.1948 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x32" "O[24]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x32" "O[24]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264124 0 0 0.264124 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x32" "O[23]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x32" "O[23]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264244 0 0 0.264244 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x32" "O[21]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x32" "O[21]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264064 0 0 0.264064 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x32" "A[5]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW256x32" "A[5]" '(0.6)
defineHierAntennaProp "SRAM1RW256x32" "A[5]" '(
("M1" 0.0366 0.738548 0 0 0.738548 0 0)
("M2" 0.0366 0.1516 20.1776 0 0.1516 0 0)
("M3" 0.0366 0.1516 24.318 0 0.1516 0 0)
("M4" 0.0366 0.1516 28.4583 0 0.1516 0 0)
("M5" 0.0366 0.1516 32.5982 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x32" "A[6]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW256x32" "A[6]" '(0.6)
defineHierAntennaProp "SRAM1RW256x32" "A[6]" '(
("M1" 0.0366 0.738548 0 0 0.738548 0 0)
("M2" 0.0366 0.1516 20.1776 0 0.1516 0 0)
("M3" 0.0366 0.1516 24.318 0 0.1516 0 0)
("M4" 0.0366 0.1516 28.4583 0 0.1516 0 0)
("M5" 0.0366 0.1516 32.5982 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x32" "A[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW256x32" "A[1]" '(0.6)
defineHierAntennaProp "SRAM1RW256x32" "A[1]" '(
("M1" 0.0366 0.738548 0 0 0.738548 0 0)
("M2" 0.0366 0.1516 20.1776 0 0.1516 0 0)
("M3" 0.0366 0.1516 24.318 0 0.1516 0 0)
("M4" 0.0366 0.1516 28.4583 0 0.1516 0 0)
("M5" 0.0366 0.1516 32.5982 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x32" "A[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW256x32" "A[0]" '(0.6)
defineHierAntennaProp "SRAM1RW256x32" "A[0]" '(
("M1" 0.0366 0.738548 0 0 0.738548 0 0)
("M2" 0.0366 0.1516 20.1776 0 0.1516 0 0)
("M3" 0.0366 0.1516 24.318 0 0.1516 0 0)
("M4" 0.0366 0.1516 28.4583 0 0.1516 0 0)
("M5" 0.0366 0.1516 32.5982 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x32" "A[3]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW256x32" "A[3]" '(0.6)
defineHierAntennaProp "SRAM1RW256x32" "A[3]" '(
("M1" 0.0366 0.738548 0 0 0.738548 0 0)
("M2" 0.0366 0.1516 20.1776 0 0.1516 0 0)
("M3" 0.0366 0.1516 24.318 0 0.1516 0 0)
("M4" 0.0366 0.1516 28.4583 0 0.1516 0 0)
("M5" 0.0366 0.1516 32.5982 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x32" "A[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW256x32" "A[2]" '(0.6)
defineHierAntennaProp "SRAM1RW256x32" "A[2]" '(
("M1" 0.0366 0.738548 0 0 0.738548 0 0)
("M2" 0.0366 0.1516 20.1776 0 0.1516 0 0)
("M3" 0.0366 0.1516 24.318 0 0.1516 0 0)
("M4" 0.0366 0.1516 28.4583 0 0.1516 0 0)
("M5" 0.0366 0.1516 32.5982 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x32" "VDD" '(0 0 0 0 1.5408 1.5408 1.5408 1.5408 1.5408 1.5408)
defineDiodeProtection "SRAM1RW256x32" "VDD" '(0 0 0 0 674.4033 674.4033 674.4033 674.4033 674.4033 674.4033)
defineHierAntennaProp "SRAM1RW256x32" "VDD" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 1.5408 9027.27 28.779 0 9027.27 0 0)
("M6" 1.5408 0 0 0 0 0 0)
("M7" 1.5408 0 0 0 0 0 0)
("M8" 1.5408 0 0 0 0 0 0)
("M9" 1.5408 0 0 0 0 0 0)
("MRDL" 1.5408 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x32" "A[4]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW256x32" "A[4]" '(0.6)
defineHierAntennaProp "SRAM1RW256x32" "A[4]" '(
("M1" 0.0366 0.738548 0 0 0.738548 0 0)
("M2" 0.0366 0.1516 20.1776 0 0.1516 0 0)
("M3" 0.0366 0.1516 24.318 0 0.1516 0 0)
("M4" 0.0366 0.1516 28.4583 0 0.1516 0 0)
("M5" 0.0366 0.1516 32.5982 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x32" "VSS" '(0 0 0 0 2.745 2.745 2.745 2.745 2.745 2.745)
defineDiodeProtection "SRAM1RW256x32" "VSS" '(0 0 0 0 861.1707 861.1707 861.1707 861.1707 861.1707 861.1707)
defineHierAntennaProp "SRAM1RW256x32" "VSS" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 2.745 9027.29 189.493 0 9027.29 0 0)
("M6" 2.745 0 0 0 0 0 0)
("M7" 2.745 0 0 0 0 0 0)
("M8" 2.745 0 0 0 0 0 0)
("M9" 2.745 0 0 0 0 0 0)
("MRDL" 2.745 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "CE" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineHierAntennaProp "SRAM1RW256x46" "CE" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0342 0.3043 3.80244 0 0.3043 0 0)
("M5" 0.0342 0.1516 12.6993 0 0.1516 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "CSB" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM1RW256x46" "CSB" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0366 0.429409 1.92428 0 0.429409 0 0)
("M5" 0.0366 0.1516 13.6559 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "I[15]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW256x46" "I[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x46" "O[30]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x46" "O[30]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "I[30]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW256x46" "I[30]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x46" "O[15]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x46" "O[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x46" "O[10]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x46" "O[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "I[10]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW256x46" "I[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x46" "O[11]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x46" "O[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "I[11]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW256x46" "I[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x46" "O[12]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x46" "O[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "I[12]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW256x46" "I[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x46" "O[42]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x46" "O[42]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "I[42]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x46" "I[42]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "I[42]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x46" "O[38]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x46" "O[38]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "I[38]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x46" "I[38]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "I[38]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x46" "O[40]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x46" "O[40]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "A[4]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW256x46" "A[4]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "A[4]" '(
("M1" 0.0366 0.644268 0 0 0.644268 0 0)
("M2" 0.0366 0.1516 17.6018 0 0.1516 0 0)
("M3" 0.0366 0.1516 21.7424 0 0.1516 0 0)
("M4" 0.0366 0.1516 25.8828 0 0.1516 0 0)
("M5" 0.0366 0.1516 30.0229 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "VSS" '(0 0 0 0 2.745 2.745 2.745 2.745 2.745 2.745)
defineDiodeProtection "SRAM1RW256x46" "VSS" '(0 0 0 0 1216.665 1216.665 1216.665 1216.665 1216.665 1216.665)
defineHierAntennaProp "SRAM1RW256x46" "VSS" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 2.745 12503.8 189.495 0 12503.8 0 0)
("M6" 2.745 0 0 0 0 0 0)
("M7" 2.745 0 0 0 0 0 0)
("M8" 2.745 0 0 0 0 0 0)
("M9" 2.745 0 0 0 0 0 0)
("MRDL" 2.745 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x46" "O[33]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x46" "O[33]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "WEB" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineDiodeProtection "SRAM1RW256x46" "WEB" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "WEB" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1461 1.57204 1.03833 0 1.57204 0 0)
("M3" 0.1461 0.1516 11.7976 0 0.1516 0 0)
("M4" 0.1461 0.1516 12.8344 0 0.1516 0 0)
("M5" 0.1461 0.1516 13.8711 0 0.1516 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "A[7]" '(0 0 0.5886 0.5886 0.5886 0.5886 0.5886 0.5886 0.5886 0.5886)
defineDiodeProtection "SRAM1RW256x46" "A[7]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "A[7]" '(
("M1" 0 1.05022 0 0 1.05022 0 0)
("M2" 0 0.173617 0 0 0.173617 0 0)
("M3" 0.5886 16.4807 15.4679 0 16.4807 0 0)
("M4" 0.5886 0.1516 43.4649 0 0.1516 0 0)
("M5" 0.5886 0.1516 43.7196 0 0.1516 0 0)
("M6" 0.5886 0 0 0 0 0 0)
("M7" 0.5886 0 0 0 0 0 0)
("M8" 0.5886 0 0 0 0 0 0)
("M9" 0.5886 0 0 0 0 0 0)
("MRDL" 0.5886 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "A[3]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW256x46" "A[3]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "A[3]" '(
("M1" 0.0366 0.644268 0 0 0.644268 0 0)
("M2" 0.0366 0.1516 17.6018 0 0.1516 0 0)
("M3" 0.0366 0.1516 21.7424 0 0.1516 0 0)
("M4" 0.0366 0.1516 25.8828 0 0.1516 0 0)
("M5" 0.0366 0.1516 30.0229 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "A[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW256x46" "A[0]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "A[0]" '(
("M1" 0.0366 0.644268 0 0 0.644268 0 0)
("M2" 0.0366 0.1516 17.6018 0 0.1516 0 0)
("M3" 0.0366 0.1516 21.7424 0 0.1516 0 0)
("M4" 0.0366 0.1516 25.8828 0 0.1516 0 0)
("M5" 0.0366 0.1516 30.0229 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "A[5]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW256x46" "A[5]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "A[5]" '(
("M1" 0.0366 0.644268 0 0 0.644268 0 0)
("M2" 0.0366 0.1516 17.6018 0 0.1516 0 0)
("M3" 0.0366 0.1516 21.7424 0 0.1516 0 0)
("M4" 0.0366 0.1516 25.8828 0 0.1516 0 0)
("M5" 0.0366 0.1516 30.0229 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "A[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW256x46" "A[1]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "A[1]" '(
("M1" 0.0366 0.644268 0 0 0.644268 0 0)
("M2" 0.0366 0.1516 17.6018 0 0.1516 0 0)
("M3" 0.0366 0.1516 21.7424 0 0.1516 0 0)
("M4" 0.0366 0.1516 25.8828 0 0.1516 0 0)
("M5" 0.0366 0.1516 30.0229 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "A[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW256x46" "A[2]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "A[2]" '(
("M1" 0.0366 0.644268 0 0 0.644268 0 0)
("M2" 0.0366 0.1516 17.6018 0 0.1516 0 0)
("M3" 0.0366 0.1516 21.7424 0 0.1516 0 0)
("M4" 0.0366 0.1516 25.8828 0 0.1516 0 0)
("M5" 0.0366 0.1516 30.0229 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "VDD" '(0 0 0 0 1.5408 1.5408 1.5408 1.5408 1.5408 1.5408)
defineDiodeProtection "SRAM1RW256x46" "VDD" '(0 0 0 0 939.4005 939.4005 939.4005 939.4005 939.4005 939.4005)
defineHierAntennaProp "SRAM1RW256x46" "VDD" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 1.5408 12503.6 28.7773 0 12503.6 0 0)
("M6" 1.5408 0 0 0 0 0 0)
("M7" 1.5408 0 0 0 0 0 0)
("M8" 1.5408 0 0 0 0 0 0)
("M9" 1.5408 0 0 0 0 0 0)
("MRDL" 1.5408 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "I[33]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x46" "I[33]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "I[33]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "I[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x46" "I[2]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "I[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "I[39]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x46" "I[39]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "I[39]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "I[36]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x46" "I[36]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "I[36]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x46" "O[35]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x46" "O[35]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "I[41]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x46" "I[41]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "I[41]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x46" "O[41]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x46" "O[41]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "I[43]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x46" "I[43]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "I[43]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x46" "O[43]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x46" "O[43]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x46" "O[39]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x46" "O[39]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "I[44]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x46" "I[44]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "I[44]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x46" "O[44]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x46" "O[44]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "I[45]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x46" "I[45]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "I[45]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x46" "O[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x46" "O[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "I[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x46" "I[1]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "I[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1514 62.3746 0 0.1514 0 0)
("M5" 0.021 0.1514 69.5795 0 0.1514 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "I[16]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x46" "I[16]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "I[16]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x46" "O[45]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x46" "O[45]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x46" "O[4]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x46" "O[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "I[4]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x46" "I[4]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "I[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x46" "O[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x46" "O[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "OEB" '(0 0.7362 0.7362 0.7362 0.7362 0.7362 0.7362 0.7362 0.7362 0.7362)
defineDiodeProtection "SRAM1RW256x46" "OEB" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "OEB" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.7362 4.03774 0.966024 0 4.03774 0 0)
("M3" 0.7362 0.1516 6.45017 0 0.1516 0 0)
("M4" 0.7362 0.1516 6.65565 0 0.1516 0 0)
("M5" 0.7362 0.1516 6.86112 0 0.1516 0 0)
("M6" 0.7362 0 0 0 0 0 0)
("M7" 0.7362 0 0 0 0 0 0)
("M8" 0.7362 0 0 0 0 0 0)
("M9" 0.7362 0 0 0 0 0 0)
("MRDL" 0.7362 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x46" "O[24]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x46" "O[24]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x46" "O[21]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x46" "O[21]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "I[24]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x46" "I[24]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "I[24]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "I[25]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x46" "I[25]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "I[25]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x46" "O[25]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x46" "O[25]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "I[21]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x46" "I[21]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "I[21]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x46" "O[18]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x46" "O[18]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "I[29]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x46" "I[29]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "I[29]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "I[18]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x46" "I[18]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "I[18]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x46" "O[16]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x46" "O[16]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "I[13]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x46" "I[13]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "I[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "I[14]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x46" "I[14]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "I[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x46" "O[13]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x46" "O[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x46" "O[14]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x46" "O[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x46" "O[29]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x46" "O[29]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "I[35]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x46" "I[35]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "I[35]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "I[37]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x46" "I[37]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "I[37]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x46" "O[36]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x46" "O[36]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x46" "O[37]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x46" "O[37]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x46" "O[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x46" "O[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "I[31]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x46" "I[31]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "I[31]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x46" "O[5]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x46" "O[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "I[5]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x46" "I[5]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "I[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "I[6]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x46" "I[6]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "I[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x46" "O[27]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x46" "O[27]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x46" "O[6]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x46" "O[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x46" "O[7]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x46" "O[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "I[7]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x46" "I[7]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "I[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "I[27]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x46" "I[27]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "I[27]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x46" "O[23]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x46" "O[23]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "I[8]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x46" "I[8]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "I[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "I[23]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x46" "I[23]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "I[23]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x46" "O[8]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x46" "O[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "I[9]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x46" "I[9]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "I[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x46" "O[22]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x46" "O[22]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "I[22]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x46" "I[22]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "I[22]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x46" "O[9]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x46" "O[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "I[17]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x46" "I[17]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "I[17]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x46" "O[19]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x46" "O[19]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "I[19]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x46" "I[19]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "I[19]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "I[40]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x46" "I[40]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "I[40]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x46" "O[17]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x46" "O[17]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x46" "O[26]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x46" "O[26]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "I[26]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x46" "I[26]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "I[26]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x46" "O[28]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x46" "O[28]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "I[28]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x46" "I[28]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "I[28]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x46" "O[20]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x46" "O[20]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "I[20]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x46" "I[20]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "I[20]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x46" "O[34]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x46" "O[34]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "I[34]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x46" "I[34]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "I[34]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x46" "O[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x46" "O[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x46" "O[31]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x46" "O[31]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "I[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x46" "I[0]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "I[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "I[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x46" "I[3]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "I[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "I[32]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x46" "I[32]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "I[32]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x46" "O[32]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x46" "O[32]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x46" "A[6]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW256x46" "A[6]" '(0.6)
defineHierAntennaProp "SRAM1RW256x46" "A[6]" '(
("M1" 0.0366 0.644268 0 0 0.644268 0 0)
("M2" 0.0366 0.1516 17.6018 0 0.1516 0 0)
("M3" 0.0366 0.1516 21.7424 0 0.1516 0 0)
("M4" 0.0366 0.1516 25.8828 0 0.1516 0 0)
("M5" 0.0366 0.1516 30.0229 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x48" "O[27]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x48" "O[27]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.273184 0 0 0.273184 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x48" "O[26]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x48" "O[26]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.273184 0 0 0.273184 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "I[28]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW256x48" "I[28]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28368 1.24826 0 1.28368 0 0)
("M4" 0.021 0.1516 62.3718 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5862 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "I[27]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW256x48" "I[27]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28368 1.24826 0 1.28368 0 0)
("M4" 0.021 0.1516 62.3718 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5862 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x48" "O[28]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x48" "O[28]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.273184 0 0 0.273184 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "A[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM1RW256x48" "A[2]" '(
("M1" 0.0366 0.643568 0 0 0.643568 0 0)
("M2" 0.0366 0.1516 17.5827 0 0.1516 0 0)
("M3" 0.0366 0.1516 21.7233 0 0.1516 0 0)
("M4" 0.0366 0.1516 25.8637 0 0.1516 0 0)
("M5" 0.0366 0.1516 30.0038 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "A[3]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM1RW256x48" "A[3]" '(
("M1" 0.0366 0.643568 0 0 0.643568 0 0)
("M2" 0.0366 0.1516 17.5827 0 0.1516 0 0)
("M3" 0.0366 0.1516 21.7233 0 0.1516 0 0)
("M4" 0.0366 0.1516 25.8637 0 0.1516 0 0)
("M5" 0.0366 0.1516 30.0038 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "A[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM1RW256x48" "A[1]" '(
("M1" 0.0366 0.643568 0 0 0.643568 0 0)
("M2" 0.0366 0.1516 17.5827 0 0.1516 0 0)
("M3" 0.0366 0.1516 21.7233 0 0.1516 0 0)
("M4" 0.0366 0.1516 25.8637 0 0.1516 0 0)
("M5" 0.0366 0.1516 30.0038 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "A[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM1RW256x48" "A[0]" '(
("M1" 0.0366 0.643568 0 0 0.643568 0 0)
("M2" 0.0366 0.1516 17.5827 0 0.1516 0 0)
("M3" 0.0366 0.1516 21.7233 0 0.1516 0 0)
("M4" 0.0366 0.1516 25.8637 0 0.1516 0 0)
("M5" 0.0366 0.1516 30.0038 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "A[6]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM1RW256x48" "A[6]" '(
("M1" 0.0366 0.643568 0 0 0.643568 0 0)
("M2" 0.0366 0.1516 17.5827 0 0.1516 0 0)
("M3" 0.0366 0.1516 21.7233 0 0.1516 0 0)
("M4" 0.0366 0.1516 25.8637 0 0.1516 0 0)
("M5" 0.0366 0.1516 30.0038 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x48" "O[17]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x48" "O[17]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.273184 0 0 0.273184 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x48" "O[16]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x48" "O[16]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.273184 0 0 0.273184 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "I[18]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x48" "I[18]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "I[18]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28368 1.24826 0 1.28368 0 0)
("M4" 0.021 0.1516 62.3718 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5862 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "I[16]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x48" "I[16]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "I[16]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28368 1.24826 0 1.28368 0 0)
("M4" 0.021 0.1516 62.3718 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5862 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "I[17]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x48" "I[17]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "I[17]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28368 1.24826 0 1.28368 0 0)
("M4" 0.021 0.1516 62.3718 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5862 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x48" "O[20]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x48" "O[20]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.273184 0 0 0.273184 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x48" "O[19]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x48" "O[19]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.273184 0 0 0.273184 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x48" "O[18]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x48" "O[18]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.273184 0 0 0.273184 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "I[21]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x48" "I[21]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "I[21]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28368 1.24826 0 1.28368 0 0)
("M4" 0.021 0.1516 62.3718 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5862 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "VDD" '(0 0 0 0 1.5408 1.5408 1.5408 1.5408 1.5408 1.5408)
defineDiodeProtection "SRAM1RW256x48" "VDD" '(0 0 0 0 977.2572 977.2572 977.2572 977.2572 977.2572 977.2572)
defineHierAntennaProp "SRAM1RW256x48" "VDD" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 1.5408 13032.4 29.167 0 13032.4 0 0)
("M6" 1.5408 0 0 0 0 0 0)
("M7" 1.5408 0 0 0 0 0 0)
("M8" 1.5408 0 0 0 0 0 0)
("M9" 1.5408 0 0 0 0 0 0)
("MRDL" 1.5408 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "I[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x48" "I[3]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "I[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28368 1.24826 0 1.28368 0 0)
("M4" 0.021 0.1516 62.3718 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5862 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x48" "O[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x48" "O[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.273184 0 0 0.273184 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "I[5]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x48" "I[5]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "I[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28368 1.24826 0 1.28368 0 0)
("M4" 0.021 0.1516 62.3718 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5862 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x48" "O[5]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x48" "O[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.273184 0 0 0.273184 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "CSB" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW256x48" "CSB" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "CSB" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0366 0.425533 2.18502 0 0.425533 0 0)
("M5" 0.0366 0.1516 13.8107 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "CE" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineDiodeProtection "SRAM1RW256x48" "CE" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "CE" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0342 0.29362 3.80961 0 0.29362 0 0)
("M5" 0.0342 0.1516 12.3942 0 0.1516 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "I[9]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x48" "I[9]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "I[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28368 1.24826 0 1.28368 0 0)
("M4" 0.021 0.1516 62.3718 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5862 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "A[7]" '(0 0 0 0.6126 0.6126 0.6126 0.6126 0.6126 0.6126 0.6126)
defineDiodeProtection "SRAM1RW256x48" "A[7]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "A[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.6126 9.34366 29.7239 0 9.34366 0 0)
("M5" 0.6126 0.1516 44.9734 0 0.1516 0 0)
("M6" 0.6126 0 0 0 0 0 0)
("M7" 0.6126 0 0 0 0 0 0)
("M8" 0.6126 0 0 0 0 0 0)
("M9" 0.6126 0 0 0 0 0 0)
("MRDL" 0.6126 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "A[4]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW256x48" "A[4]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "A[4]" '(
("M1" 0.0366 0.643568 0 0 0.643568 0 0)
("M2" 0.0366 0.1516 17.5827 0 0.1516 0 0)
("M3" 0.0366 0.1516 21.7233 0 0.1516 0 0)
("M4" 0.0366 0.1516 25.8637 0 0.1516 0 0)
("M5" 0.0366 0.1516 30.0038 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "WEB" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineDiodeProtection "SRAM1RW256x48" "WEB" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "WEB" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1461 1.57126 1.03833 0 1.57126 0 0)
("M3" 0.1461 0.1516 11.7922 0 0.1516 0 0)
("M4" 0.1461 0.1516 12.829 0 0.1516 0 0)
("M5" 0.1461 0.1516 13.8658 0 0.1516 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "A[5]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW256x48" "A[5]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "A[5]" '(
("M1" 0.0366 0.643568 0 0 0.643568 0 0)
("M2" 0.0366 0.1516 17.5827 0 0.1516 0 0)
("M3" 0.0366 0.1516 21.7233 0 0.1516 0 0)
("M4" 0.0366 0.1516 25.8637 0 0.1516 0 0)
("M5" 0.0366 0.1516 30.0038 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "VSS" '(0 0 0 0 2.745 2.745 2.745 2.745 2.745 2.745)
defineDiodeProtection "SRAM1RW256x48" "VSS" '(0 0 0 0 1268.452 1268.452 1268.452 1268.452 1268.452 1268.452)
defineHierAntennaProp "SRAM1RW256x48" "VSS" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 2.745 13032.4 116.941 0 13032.4 0 0)
("M6" 2.745 0 0 0 0 0 0)
("M7" 2.745 0 0 0 0 0 0)
("M8" 2.745 0 0 0 0 0 0)
("M9" 2.745 0 0 0 0 0 0)
("MRDL" 2.745 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x48" "O[38]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x48" "O[38]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.273184 0 0 0.273184 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "I[39]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x48" "I[39]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "I[39]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28368 1.24826 0 1.28368 0 0)
("M4" 0.021 0.1516 62.3718 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5862 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x48" "O[39]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x48" "O[39]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.273184 0 0 0.273184 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "I[40]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x48" "I[40]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "I[40]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28368 1.24826 0 1.28368 0 0)
("M4" 0.021 0.1516 62.3718 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5862 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x48" "O[40]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x48" "O[40]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.273184 0 0 0.273184 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "I[41]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x48" "I[41]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "I[41]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28368 1.24826 0 1.28368 0 0)
("M4" 0.021 0.1516 62.3718 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5862 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x48" "O[41]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x48" "O[41]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.273184 0 0 0.273184 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "I[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x48" "I[2]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "I[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28368 1.24826 0 1.28368 0 0)
("M4" 0.021 0.1516 62.3718 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5862 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x48" "O[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x48" "O[2]" '(
("M1" 0 0.1536 0 0 0.1536 0 0)
("M2" 0 0.1536 0 0 0.1536 0 0)
("M3" 0 0.274584 0 0 0.274584 0 0)
("M4" 0 0.1536 0 0 0.1536 0 0)
("M5" 0 0.1536 0 0 0.1536 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x48" "O[42]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x48" "O[42]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.273184 0 0 0.273184 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "I[44]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x48" "I[44]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "I[44]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28368 1.24826 0 1.28368 0 0)
("M4" 0.021 0.1516 62.3718 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5862 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x48" "O[44]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x48" "O[44]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.273184 0 0 0.273184 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "I[46]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x48" "I[46]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "I[46]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28368 1.24826 0 1.28368 0 0)
("M4" 0.021 0.1516 62.3718 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5862 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "I[47]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x48" "I[47]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "I[47]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28368 1.24826 0 1.28368 0 0)
("M4" 0.021 0.1516 62.3718 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5862 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x48" "O[47]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x48" "O[47]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.273184 0 0 0.273184 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x48" "O[33]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x48" "O[33]" '(
("M1" 0 0.1412 0 0 0.1412 0 0)
("M2" 0 0.1412 0 0 0.1412 0 0)
("M3" 0 0.265904 0 0 0.265904 0 0)
("M4" 0 0.1412 0 0 0.1412 0 0)
("M5" 0 0.1412 0 0 0.1412 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "I[34]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x48" "I[34]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "I[34]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28368 1.24826 0 1.28368 0 0)
("M4" 0.021 0.1516 62.3718 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5862 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x48" "O[34]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x48" "O[34]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.273184 0 0 0.273184 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "I[43]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x48" "I[43]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "I[43]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28368 1.24826 0 1.28368 0 0)
("M4" 0.021 0.1516 62.3718 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5862 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x48" "O[43]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x48" "O[43]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.273184 0 0 0.273184 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "I[35]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x48" "I[35]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "I[35]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28368 1.24826 0 1.28368 0 0)
("M4" 0.021 0.1516 62.3718 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5862 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x48" "O[35]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x48" "O[35]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.273184 0 0 0.273184 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "I[36]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x48" "I[36]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "I[36]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28368 1.24826 0 1.28368 0 0)
("M4" 0.021 0.1516 62.3718 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5862 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x48" "O[36]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x48" "O[36]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.273184 0 0 0.273184 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "I[37]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x48" "I[37]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "I[37]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28368 1.24826 0 1.28368 0 0)
("M4" 0.021 0.1516 62.3718 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5862 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x48" "O[37]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x48" "O[37]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.273184 0 0 0.273184 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "I[38]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x48" "I[38]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "I[38]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28368 1.24826 0 1.28368 0 0)
("M4" 0.021 0.1516 62.3718 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5862 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "I[8]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x48" "I[8]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "I[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28368 1.24826 0 1.28368 0 0)
("M4" 0.021 0.1516 62.3718 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5862 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "I[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x48" "I[1]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "I[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28368 1.24826 0 1.28368 0 0)
("M4" 0.021 0.1516 62.3718 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5862 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x48" "O[14]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x48" "O[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.273184 0 0 0.273184 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x48" "O[15]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x48" "O[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.273184 0 0 0.273184 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x48" "O[9]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x48" "O[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.273184 0 0 0.273184 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "I[11]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x48" "I[11]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "I[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28368 1.24826 0 1.28368 0 0)
("M4" 0.021 0.1516 62.3718 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5862 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "I[15]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x48" "I[15]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "I[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28368 1.24826 0 1.28368 0 0)
("M4" 0.021 0.1516 62.3718 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5862 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "OEB" '(0 0.7674 0.7674 0.7674 0.7674 0.7674 0.7674 0.7674 0.7674 0.7674)
defineDiodeProtection "SRAM1RW256x48" "OEB" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "OEB" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.7674 4.19632 0.966024 0 4.19632 0 0)
("M3" 0.7674 0.1516 6.43383 0 0.1516 0 0)
("M4" 0.7674 0.1516 6.63094 0 0.1516 0 0)
("M5" 0.7674 0.1516 6.82804 0 0.1516 0 0)
("M6" 0.7674 0 0 0 0 0 0)
("M7" 0.7674 0 0 0 0 0 0)
("M8" 0.7674 0 0 0 0 0 0)
("M9" 0.7674 0 0 0 0 0 0)
("MRDL" 0.7674 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x48" "O[32]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x48" "O[32]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.273184 0 0 0.273184 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x48" "O[12]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x48" "O[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.273184 0 0 0.273184 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x48" "O[11]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x48" "O[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.273184 0 0 0.273184 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "I[32]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x48" "I[32]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "I[32]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28368 1.24826 0 1.28368 0 0)
("M4" 0.021 0.1516 62.3718 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5862 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "I[12]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x48" "I[12]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "I[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28368 1.24826 0 1.28368 0 0)
("M4" 0.021 0.1516 62.3718 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5862 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x48" "O[45]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x48" "O[45]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.273184 0 0 0.273184 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "I[45]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x48" "I[45]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "I[45]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28368 1.24826 0 1.28368 0 0)
("M4" 0.021 0.1516 62.3718 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5862 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x48" "O[31]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x48" "O[31]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.273184 0 0 0.273184 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "I[31]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x48" "I[31]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "I[31]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28368 1.24826 0 1.28368 0 0)
("M4" 0.021 0.1516 62.3718 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5862 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "I[23]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x48" "I[23]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "I[23]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28368 1.24826 0 1.28368 0 0)
("M4" 0.021 0.1516 62.3718 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5862 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "I[42]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x48" "I[42]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "I[42]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28368 1.24826 0 1.28368 0 0)
("M4" 0.021 0.1516 62.3718 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5862 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "I[29]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x48" "I[29]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "I[29]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28368 1.24826 0 1.28368 0 0)
("M4" 0.021 0.1516 62.3718 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5862 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x48" "O[29]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x48" "O[29]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.273184 0 0 0.273184 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x48" "O[7]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x48" "O[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.273184 0 0 0.273184 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x48" "O[46]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x48" "O[46]" '(
("M1" 0 0.1514 0 0 0.1514 0 0)
("M2" 0 0.1514 0 0 0.1514 0 0)
("M3" 0 0.273044 0 0 0.273044 0 0)
("M4" 0 0.1514 0 0 0.1514 0 0)
("M5" 0 0.1514 0 0 0.1514 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x48" "O[30]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x48" "O[30]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.273184 0 0 0.273184 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "I[7]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x48" "I[7]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "I[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28368 1.24826 0 1.28368 0 0)
("M4" 0.021 0.1516 62.3718 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5862 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "I[33]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x48" "I[33]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "I[33]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28368 1.24826 0 1.28368 0 0)
("M4" 0.021 0.1516 62.3718 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5862 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "I[30]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x48" "I[30]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "I[30]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28368 1.24826 0 1.28368 0 0)
("M4" 0.021 0.1516 62.3718 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5862 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x48" "O[6]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x48" "O[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.273184 0 0 0.273184 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x48" "O[13]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x48" "O[13]" '(
("M1" 0 0.1536 0 0 0.1536 0 0)
("M2" 0 0.1536 0 0 0.1536 0 0)
("M3" 0 0.274584 0 0 0.274584 0 0)
("M4" 0 0.1536 0 0 0.1536 0 0)
("M5" 0 0.1536 0 0 0.1536 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x48" "O[4]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x48" "O[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.273184 0 0 0.273184 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "I[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x48" "I[0]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "I[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28368 1.24826 0 1.28368 0 0)
("M4" 0.021 0.1516 62.3718 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5862 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "I[6]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x48" "I[6]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "I[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28368 1.24826 0 1.28368 0 0)
("M4" 0.021 0.1516 62.3718 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5862 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "I[13]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x48" "I[13]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "I[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28368 1.24826 0 1.28368 0 0)
("M4" 0.021 0.1516 62.3718 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5862 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "I[4]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x48" "I[4]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "I[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28368 1.24826 0 1.28368 0 0)
("M4" 0.021 0.1516 62.3718 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5862 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x48" "O[8]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x48" "O[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.273184 0 0 0.273184 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x48" "O[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x48" "O[1]" '(
("M1" 0 0.1412 0 0 0.1412 0 0)
("M2" 0 0.1412 0 0 0.1412 0 0)
("M3" 0 0.265904 0 0 0.265904 0 0)
("M4" 0 0.1412 0 0 0.1412 0 0)
("M5" 0 0.1412 0 0 0.1412 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x48" "O[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x48" "O[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.273184 0 0 0.273184 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "I[14]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x48" "I[14]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "I[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28368 1.24826 0 1.28368 0 0)
("M4" 0.021 0.1516 62.3718 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5862 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "I[20]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x48" "I[20]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "I[20]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28368 1.24826 0 1.28368 0 0)
("M4" 0.021 0.1516 62.3718 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5862 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "I[19]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x48" "I[19]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "I[19]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28368 1.24826 0 1.28368 0 0)
("M4" 0.021 0.1516 62.3718 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5862 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x48" "O[22]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x48" "O[22]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.273184 0 0 0.273184 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x48" "O[10]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x48" "O[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.273184 0 0 0.273184 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x48" "O[21]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x48" "O[21]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.273184 0 0 0.273184 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "I[22]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x48" "I[22]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "I[22]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28368 1.24826 0 1.28368 0 0)
("M4" 0.021 0.1516 62.3718 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5862 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "I[10]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x48" "I[10]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "I[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28368 1.24826 0 1.28368 0 0)
("M4" 0.021 0.1516 62.3718 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5862 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x48" "O[25]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x48" "O[25]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.273184 0 0 0.273184 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x48" "O[24]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x48" "O[24]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.273184 0 0 0.273184 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x48" "O[23]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x48" "O[23]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.273184 0 0 0.273184 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "I[26]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x48" "I[26]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "I[26]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28368 1.24826 0 1.28368 0 0)
("M4" 0.021 0.1516 62.3718 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5862 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "I[25]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x48" "I[25]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "I[25]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28368 1.24826 0 1.28368 0 0)
("M4" 0.021 0.1516 62.3718 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5862 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x48" "I[24]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x48" "I[24]" '(0.6)
defineHierAntennaProp "SRAM1RW256x48" "I[24]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28368 1.24826 0 1.28368 0 0)
("M4" 0.021 0.1516 62.3718 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5862 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[15]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW256x128" "I[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[14]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[14]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW256x128" "I[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[16]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW256x128" "I[16]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[15]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[16]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[16]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[17]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW256x128" "I[17]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[11]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW256x128" "I[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[11]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[13]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW256x128" "I[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[13]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[12]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[12]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[12]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[7]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[8]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[8]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[9]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[9]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[8]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[10]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[10]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[24]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[24]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[24]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[24]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[24]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[25]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[25]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[25]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[27]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[27]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[27]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[26]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[26]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[25]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[25]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[26]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[26]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[26]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[20]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[20]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[21]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[21]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[21]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[21]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[21]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[22]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[22]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[23]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[23]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[23]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[22]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[22]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[22]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[18]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[18]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[18]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[17]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[17]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[20]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[20]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[20]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[19]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[19]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[19]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[19]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[19]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[47]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[47]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[44]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[44]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[62]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[62]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[62]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[62]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[62]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[64]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[64]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[64]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[64]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[64]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[58]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[58]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[58]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[58]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[58]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[60]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[60]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[60]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[61]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[61]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[59]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[59]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[59]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[59]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[59]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[61]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[61]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[61]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[60]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[60]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[57]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[57]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[56]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[56]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[56]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[56]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[56]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[57]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[57]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[57]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[55]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[55]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[54]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[54]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[55]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[55]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[55]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[74]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[74]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[74]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[72]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[72]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[72]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[71]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[71]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[71]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[71]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[71]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[70]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[70]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[68]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[68]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[68]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[70]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[70]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[70]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[69]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[69]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[69]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[69]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[69]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[68]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[68]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[65]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[65]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[65]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[65]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[65]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[66]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[66]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[66]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[67]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[67]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[67]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[67]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[67]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[66]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[66]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[63]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[63]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[63]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[63]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[63]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "CE" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineDiodeProtection "SRAM1RW256x128" "CE" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "CE" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0342 0.3181 3.80244 0 0.3181 0 0)
("M5" 0.0342 0.1516 13.1028 0 0.1516 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[48]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[48]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[48]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[81]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[81]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[79]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[79]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[81]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[81]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[81]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[79]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[79]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[79]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[80]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[80]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[80]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[80]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[80]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[77]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[77]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[78]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[78]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[78]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[78]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[78]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[77]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[77]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[77]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[75]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[75]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[75]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[75]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[75]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[76]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[76]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[76]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[76]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[76]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[72]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[72]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[73]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[73]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[73]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[73]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[73]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[74]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[74]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[9]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[10]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[5]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[5]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[5]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[4]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[6]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[6]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[6]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[7]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[7]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[3]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[4]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[4]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[1]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1514 62.3746 0 0.1514 0 0)
("M5" 0.021 0.1514 69.5795 0 0.1514 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[0]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "OEB" '(0 2.0154 2.0154 2.0154 2.0154 2.0154 2.0154 2.0154 2.0154 2.0154)
defineDiodeProtection "SRAM1RW256x128" "OEB" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "OEB" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 2.0154 10.7672 0.966025 0 10.7672 0 0)
("M3" 2.0154 0.1516 6.30805 0 0.1516 0 0)
("M4" 2.0154 0.1516 6.38285 0 0.1516 0 0)
("M5" 2.0154 0.1516 6.45765 0 0.1516 0 0)
("M6" 2.0154 0 0 0 0 0 0)
("M7" 2.0154 0 0 0 0 0 0)
("M8" 2.0154 0 0 0 0 0 0)
("M9" 2.0154 0 0 0 0 0 0)
("MRDL" 2.0154 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "A[7]" '(0 0 0 1.5726 1.5726 1.5726 1.5726 1.5726 1.5726 1.5726)
defineDiodeProtection "SRAM1RW256x128" "A[7]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "A[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 1.5726 22.489 30.1958 0 22.489 0 0)
("M5" 1.5726 0.1516 44.4934 0 0.1516 0 0)
("M6" 1.5726 0 0 0 0 0 0)
("M7" 1.5726 0 0 0 0 0 0)
("M8" 1.5726 0 0 0 0 0 0)
("M9" 1.5726 0 0 0 0 0 0)
("MRDL" 1.5726 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[18]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[18]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[113]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[113]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "A[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW256x128" "A[1]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "A[1]" '(
("M1" 0.0366 0.655768 0 0 0.655768 0 0)
("M2" 0.0366 0.1516 17.916 0 0.1516 0 0)
("M3" 0.0366 0.1516 22.0566 0 0.1516 0 0)
("M4" 0.0366 0.1516 26.1969 0 0.1516 0 0)
("M5" 0.0366 0.1516 30.337 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "A[6]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW256x128" "A[6]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "A[6]" '(
("M1" 0.0366 0.655768 0 0 0.655768 0 0)
("M2" 0.0366 0.1516 17.916 0 0.1516 0 0)
("M3" 0.0366 0.1516 22.0566 0 0.1516 0 0)
("M4" 0.0366 0.1516 26.1969 0 0.1516 0 0)
("M5" 0.0366 0.1516 30.337 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "CSB" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW256x128" "CSB" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "CSB" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0366 0.443209 1.92429 0 0.443209 0 0)
("M5" 0.0366 0.1516 14.0329 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[2]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[126]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[126]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[127]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[127]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[127]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[127]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[127]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[124]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[124]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[126]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[126]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[126]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[124]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[124]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[124]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[125]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[125]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[125]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[123]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[123]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[125]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[125]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[121]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[121]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[123]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[123]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[123]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[121]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[121]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[121]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[120]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[120]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "VSS" '(0 0 0 0 2.745 2.745 2.745 2.745 2.745 2.745)
defineDiodeProtection "SRAM1RW256x128" "VSS" '(0 0 0 0 3285.312 3285.312 3285.312 3285.312 3285.312 3285.312)
defineHierAntennaProp "SRAM1RW256x128" "VSS" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 2.745 36971.7 112.164 0 36971.7 0 0)
("M6" 2.745 0 0 0 0 0 0)
("M7" 2.745 0 0 0 0 0 0)
("M8" 2.745 0 0 0 0 0 0)
("M9" 2.745 0 0 0 0 0 0)
("MRDL" 2.745 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "A[5]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW256x128" "A[5]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "A[5]" '(
("M1" 0.0366 0.655768 0 0 0.655768 0 0)
("M2" 0.0366 0.1516 17.916 0 0.1516 0 0)
("M3" 0.0366 0.1516 22.0566 0 0.1516 0 0)
("M4" 0.0366 0.1516 26.1969 0 0.1516 0 0)
("M5" 0.0366 0.1516 30.337 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "A[4]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW256x128" "A[4]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "A[4]" '(
("M1" 0.0366 0.655768 0 0 0.655768 0 0)
("M2" 0.0366 0.1516 17.916 0 0.1516 0 0)
("M3" 0.0366 0.1516 22.0566 0 0.1516 0 0)
("M4" 0.0366 0.1516 26.1969 0 0.1516 0 0)
("M5" 0.0366 0.1516 30.337 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "A[3]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW256x128" "A[3]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "A[3]" '(
("M1" 0.0366 0.655768 0 0 0.655768 0 0)
("M2" 0.0366 0.1516 17.916 0 0.1516 0 0)
("M3" 0.0366 0.1516 22.0566 0 0.1516 0 0)
("M4" 0.0366 0.1516 26.1969 0 0.1516 0 0)
("M5" 0.0366 0.1516 30.337 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "A[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW256x128" "A[2]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "A[2]" '(
("M1" 0.0366 0.655768 0 0 0.655768 0 0)
("M2" 0.0366 0.1516 17.916 0 0.1516 0 0)
("M3" 0.0366 0.1516 22.0566 0 0.1516 0 0)
("M4" 0.0366 0.1516 26.1969 0 0.1516 0 0)
("M5" 0.0366 0.1516 30.337 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "A[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW256x128" "A[0]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "A[0]" '(
("M1" 0.0366 0.655768 0 0 0.655768 0 0)
("M2" 0.0366 0.1516 17.916 0 0.1516 0 0)
("M3" 0.0366 0.1516 22.0566 0 0.1516 0 0)
("M4" 0.0366 0.1516 26.1969 0 0.1516 0 0)
("M5" 0.0366 0.1516 30.337 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "VDD" '(0 0 0 0 1.5408 1.5408 1.5408 1.5408 1.5408 1.5408)
defineDiodeProtection "SRAM1RW256x128" "VDD" '(0 0 0 0 2491.527 2491.527 2491.527 2491.527 2491.527 2491.527)
defineHierAntennaProp "SRAM1RW256x128" "VDD" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 1.5408 36885.5 29.2626 0 36885.5 0 0)
("M6" 1.5408 0 0 0 0 0 0)
("M7" 1.5408 0 0 0 0 0 0)
("M8" 1.5408 0 0 0 0 0 0)
("M9" 1.5408 0 0 0 0 0 0)
("MRDL" 1.5408 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[37]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[37]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[38]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[38]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[38]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[31]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[31]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[32]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[32]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[32]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[32]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[32]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[33]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[33]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[34]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[34]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[34]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[35]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[35]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[35]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[33]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[33]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[33]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[34]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[34]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[27]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[27]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[29]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[29]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[29]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[28]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[28]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[29]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[29]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[30]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[30]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[30]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[28]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[28]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[28]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[31]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[31]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[31]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[30]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[30]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[23]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[23]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[42]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[42]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[43]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[43]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[43]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[43]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[43]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[44]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[44]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[44]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[45]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[45]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[45]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[45]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[45]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[39]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[39]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[39]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[39]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[39]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[42]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[42]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[42]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[40]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[40]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[40]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[40]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[40]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[41]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[41]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[41]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[41]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[41]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[36]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[36]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[36]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[35]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[35]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[36]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[36]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[37]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[37]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[37]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[38]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[38]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[53]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[53]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[53]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[52]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[52]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[54]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[54]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[54]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[53]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[53]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[52]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[52]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[52]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[51]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[51]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[50]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[50]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[50]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[50]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[50]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[51]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[51]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[51]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[48]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[48]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[49]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[49]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[49]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[49]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[49]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "WEB" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineDiodeProtection "SRAM1RW256x128" "WEB" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "WEB" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1461 1.58584 1.03834 0 1.58584 0 0)
("M3" 0.1461 0.1516 11.892 0 0.1516 0 0)
("M4" 0.1461 0.1516 12.9288 0 0.1516 0 0)
("M5" 0.1461 0.1516 13.9656 0 0.1516 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[46]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[46]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[46]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[46]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[46]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[47]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[47]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[47]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1514 62.3746 0 0.1514 0 0)
("M5" 0.021 0.1514 69.5795 0 0.1514 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[84]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[84]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[84]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[85]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[85]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[82]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[82]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[82]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[82]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[82]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[83]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[83]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[83]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[92]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[92]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[92]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[92]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[92]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[93]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[93]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[93]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1514 62.3746 0 0.1514 0 0)
("M5" 0.021 0.1514 69.5795 0 0.1514 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[90]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[90]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[90]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[90]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[90]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[91]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[91]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[91]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[91]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[91]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[87]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[87]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[87]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[86]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[86]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[88]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[88]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[88]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[87]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[87]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[88]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[88]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[89]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[89]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[89]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[89]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[89]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[86]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[86]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[86]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[84]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[84]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[83]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[83]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[85]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[85]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[85]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[102]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[102]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[102]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[102]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[102]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[100]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[100]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[101]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[101]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[101]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[101]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[101]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[98]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[98]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[99]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[99]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[99]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[100]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[100]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[100]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[99]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[99]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[97]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[97]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[98]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[98]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[98]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[96]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[96]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[97]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[97]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[97]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[96]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[96]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[96]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[95]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[95]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[95]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[95]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[95]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[94]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[94]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[94]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[94]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[94]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[93]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[93]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[114]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[114]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[110]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[110]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[110]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[110]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[110]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[111]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[111]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[111]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[111]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[111]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[109]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[109]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[109]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[109]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[109]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[107]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[107]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[108]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[108]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[108]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[108]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[108]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[106]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[106]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[106]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[107]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[107]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[107]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[106]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[106]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[105]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[105]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[104]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[104]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[104]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[104]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[104]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[105]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[105]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[105]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[103]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[103]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[103]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[103]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[103]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[122]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[122]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[122]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[122]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[122]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[118]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[118]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[118]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[118]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[118]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[120]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[120]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[120]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[119]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[119]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[119]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[119]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[119]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[117]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[117]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[117]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[117]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[117]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[115]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[115]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[115]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[115]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[115]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[116]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[116]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[116]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[116]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[116]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[113]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[113]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[113]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW256x128" "O[112]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW256x128" "O[112]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[114]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[114]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[114]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW256x128" "I[112]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW256x128" "I[112]" '(0.6)
defineHierAntennaProp "SRAM1RW256x128" "I[112]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x8" "O[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x8" "O[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271144 0 0 0.271144 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x8" "WEB" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineHierAntennaProp "SRAM1RW512x8" "WEB" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1461 1.80586 1.03833 0 1.80586 0 0)
("M3" 0.1461 0.1516 13.3979 0 0.1516 0 0)
("M4" 0.1461 0.1516 14.4346 0 0.1516 0 0)
("M5" 0.1461 0.1516 15.4712 0 0.1516 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x8" "O[4]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x8" "O[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271084 0 0 0.271084 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x8" "I[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW512x8" "I[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28161 1.24826 0 1.28161 0 0)
("M4" 0.021 0.1516 62.2733 0 0.1516 0 0)
("M5" 0.021 0.1516 69.4878 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x8" "I[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW512x8" "I[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28161 1.24826 0 1.28161 0 0)
("M4" 0.021 0.1516 62.2733 0 0.1516 0 0)
("M5" 0.021 0.1516 69.4878 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x8" "I[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW512x8" "I[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28161 1.24826 0 1.28161 0 0)
("M4" 0.021 0.1516 62.2733 0 0.1516 0 0)
("M5" 0.021 0.1516 69.4878 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x8" "O[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x8" "O[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.270904 0 0 0.270904 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x8" "I[4]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW512x8" "I[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28161 1.24826 0 1.28161 0 0)
("M4" 0.021 0.1516 62.2733 0 0.1516 0 0)
("M5" 0.021 0.1516 69.4878 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x8" "I[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW512x8" "I[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28161 1.24826 0 1.28161 0 0)
("M4" 0.021 0.1516 62.2733 0 0.1516 0 0)
("M5" 0.021 0.1516 69.4878 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x8" "I[7]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW512x8" "I[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28161 1.24826 0 1.28161 0 0)
("M4" 0.021 0.1516 62.2733 0 0.1516 0 0)
("M5" 0.021 0.1516 69.4878 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x8" "O[7]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x8" "O[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271084 0 0 0.271084 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x8" "I[5]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW512x8" "I[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28161 1.24826 0 1.28161 0 0)
("M4" 0.021 0.1516 62.2733 0 0.1516 0 0)
("M5" 0.021 0.1516 69.4878 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x8" "CSB" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM1RW512x8" "CSB" '(
("M1" 0.0366 0.71736 0 0 0.71736 0 0)
("M2" 0.0366 0.1516 19.5987 0 0.1516 0 0)
("M3" 0.0366 0.1516 23.7392 0 0.1516 0 0)
("M4" 0.0366 0.1516 27.8795 0 0.1516 0 0)
("M5" 0.0366 0.1516 32.0194 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x8" "O[5]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x8" "O[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.270828 0 0 0.270828 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x8" "O[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x8" "O[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271444 0 0 0.271444 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x8" "O[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x8" "O[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271084 0 0 0.271084 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x8" "A[5]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW512x8" "A[5]" '(0.6)
defineHierAntennaProp "SRAM1RW512x8" "A[5]" '(
("M1" 0.0366 0.291918 0 0 0.291918 0 0)
("M2" 0.0366 0.1516 7.97537 0 0.1516 0 0)
("M3" 0.0366 0.1516 12.1167 0 0.1516 0 0)
("M4" 0.0366 0.1516 16.2577 0 0.1516 0 0)
("M5" 0.0366 0.1516 20.3984 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x8" "OEB" '(0 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434)
defineDiodeProtection "SRAM1RW512x8" "OEB" '(0.6)
defineHierAntennaProp "SRAM1RW512x8" "OEB" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1434 0.91576 0.966015 0 0.91576 0 0)
("M3" 0.1434 0.1516 7.35158 0 0.1516 0 0)
("M4" 0.1434 0.1516 8.40821 0 0.1516 0 0)
("M5" 0.1434 0.1516 9.46477 0 0.1516 0 0)
("M6" 0.1434 0 0 0 0 0 0)
("M7" 0.1434 0 0 0 0 0 0)
("M8" 0.1434 0 0 0 0 0 0)
("M9" 0.1434 0 0 0 0 0 0)
("MRDL" 0.1434 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x8" "O[6]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x8" "O[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271264 0 0 0.271264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x8" "CE" '(0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineDiodeProtection "SRAM1RW512x8" "CE" '(0.6)
defineHierAntennaProp "SRAM1RW512x8" "CE" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.46132 0 0 0.46132 0 0)
("M3" 0.0342 0.29578 1.87136 0 0.29578 0 0)
("M4" 0.0342 0.1516 10.5192 0 0.1516 0 0)
("M5" 0.0342 0.1516 14.951 0 0.1516 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x8" "A[8]" '(0 0 0 0.0732 0.0732 0.0732 0.0732 0.0732 0.0732 0.0732)
defineDiodeProtection "SRAM1RW512x8" "A[8]" '(0.6)
defineHierAntennaProp "SRAM1RW512x8" "A[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0732 3.91402 2.10079 0 3.91402 0 0)
("M5" 0.0732 0.1516 55.5673 0 0.1516 0 0)
("M6" 0.0732 0 0 0 0 0 0)
("M7" 0.0732 0 0 0 0 0 0)
("M8" 0.0732 0 0 0 0 0 0)
("M9" 0.0732 0 0 0 0 0 0)
("MRDL" 0.0732 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x8" "A[4]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW512x8" "A[4]" '(0.6)
defineHierAntennaProp "SRAM1RW512x8" "A[4]" '(
("M1" 0.0366 0.291918 0 0 0.291918 0 0)
("M2" 0.0366 0.1516 7.97537 0 0.1516 0 0)
("M3" 0.0366 0.1516 12.1167 0 0.1516 0 0)
("M4" 0.0366 0.1516 16.2577 0 0.1516 0 0)
("M5" 0.0366 0.1516 20.3984 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x8" "A[3]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW512x8" "A[3]" '(0.6)
defineHierAntennaProp "SRAM1RW512x8" "A[3]" '(
("M1" 0.0366 0.291918 0 0 0.291918 0 0)
("M2" 0.0366 0.1516 7.97537 0 0.1516 0 0)
("M3" 0.0366 0.1516 12.1167 0 0.1516 0 0)
("M4" 0.0366 0.1516 16.2577 0 0.1516 0 0)
("M5" 0.0366 0.1516 20.3984 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x8" "A[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW512x8" "A[2]" '(0.6)
defineHierAntennaProp "SRAM1RW512x8" "A[2]" '(
("M1" 0.0366 0.291918 0 0 0.291918 0 0)
("M2" 0.0366 0.1516 7.97537 0 0.1516 0 0)
("M3" 0.0366 0.1516 12.1167 0 0.1516 0 0)
("M4" 0.0366 0.1516 16.2577 0 0.1516 0 0)
("M5" 0.0366 0.1516 20.3984 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x8" "A[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW512x8" "A[1]" '(0.6)
defineHierAntennaProp "SRAM1RW512x8" "A[1]" '(
("M1" 0.0366 0.291918 0 0 0.291918 0 0)
("M2" 0.0366 0.1516 7.97537 0 0.1516 0 0)
("M3" 0.0366 0.1516 12.1167 0 0.1516 0 0)
("M4" 0.0366 0.1516 16.2577 0 0.1516 0 0)
("M5" 0.0366 0.1516 20.3984 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x8" "A[7]" '(0 0 0 0.0732 0.0732 0.0732 0.0732 0.0732 0.0732 0.0732)
defineDiodeProtection "SRAM1RW512x8" "A[7]" '(0.6)
defineHierAntennaProp "SRAM1RW512x8" "A[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0732 3.91498 3.14059 0 3.91498 0 0)
("M5" 0.0732 0.1516 56.6202 0 0.1516 0 0)
("M6" 0.0732 0 0 0 0 0 0)
("M7" 0.0732 0 0 0 0 0 0)
("M8" 0.0732 0 0 0 0 0 0)
("M9" 0.0732 0 0 0 0 0 0)
("MRDL" 0.0732 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x8" "A[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW512x8" "A[0]" '(0.6)
defineHierAntennaProp "SRAM1RW512x8" "A[0]" '(
("M1" 0.0366 0.291918 0 0 0.291918 0 0)
("M2" 0.0366 0.1516 7.97537 0 0.1516 0 0)
("M3" 0.0366 0.1516 12.1167 0 0.1516 0 0)
("M4" 0.0366 0.1516 16.2577 0 0.1516 0 0)
("M5" 0.0366 0.1516 20.3984 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x8" "I[6]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x8" "I[6]" '(0.6)
defineHierAntennaProp "SRAM1RW512x8" "I[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28161 1.24826 0 1.28161 0 0)
("M4" 0.021 0.1516 62.2733 0 0.1516 0 0)
("M5" 0.021 0.1516 69.4878 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x8" "A[6]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW512x8" "A[6]" '(0.6)
defineHierAntennaProp "SRAM1RW512x8" "A[6]" '(
("M1" 0.0366 0.291918 0 0 0.291918 0 0)
("M2" 0.0366 0.1516 7.97537 0 0.1516 0 0)
("M3" 0.0366 0.1516 12.1167 0 0.1516 0 0)
("M4" 0.0366 0.1516 16.2577 0 0.1516 0 0)
("M5" 0.0366 0.1516 20.3984 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x8" "VDD" '(0 0 0 0 1.5408 1.5408 1.5408 1.5408 1.5408 1.5408)
defineDiodeProtection "SRAM1RW512x8" "VDD" '(0 0 0 0 362.332 362.332 362.332 362.332 362.332 362.332)
defineHierAntennaProp "SRAM1RW512x8" "VDD" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 1.5408 5035.81 29.1677 0 5035.81 0 0)
("M6" 1.5408 0 0 0 0 0 0)
("M7" 1.5408 0 0 0 0 0 0)
("M8" 1.5408 0 0 0 0 0 0)
("M9" 1.5408 0 0 0 0 0 0)
("MRDL" 1.5408 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x8" "VSS" '(0 0 0 0 2.745 2.745 2.745 2.745 2.745 2.745)
defineDiodeProtection "SRAM1RW512x8" "VSS" '(0 0 0 0 447.5562 447.5562 447.5562 447.5562 447.5562 447.5562)
defineHierAntennaProp "SRAM1RW512x8" "VSS" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 2.745 4965.88 115.455 0 4965.88 0 0)
("M6" 2.745 0 0 0 0 0 0)
("M7" 2.745 0 0 0 0 0 0)
("M8" 2.745 0 0 0 0 0 0)
("M9" 2.745 0 0 0 0 0 0)
("MRDL" 2.745 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x32" "VDD" '(0 0 0 0 1.5408 1.5408 1.5408 1.5408 1.5408 1.5408)
defineDiodeProtection "SRAM1RW512x32" "VDD" '(0 0 0 0 1239.328 1239.328 1239.328 1239.328 1239.328 1239.328)
defineHierAntennaProp "SRAM1RW512x32" "VDD" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 1.5408 16723.6 144.511 0 16723.6 0 0)
("M6" 1.5408 0 0 0 0 0 0)
("M7" 1.5408 0 0 0 0 0 0)
("M8" 1.5408 0 0 0 0 0 0)
("M9" 1.5408 0 0 0 0 0 0)
("MRDL" 1.5408 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x32" "I[11]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW512x32" "I[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x32" "O[31]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x32" "O[31]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271444 0 0 0.271444 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x32" "I[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW512x32" "I[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x32" "I[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW512x32" "I[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x32" "O[10]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x32" "O[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271144 0 0 0.271144 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x32" "I[31]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW512x32" "I[31]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x32" "I[30]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW512x32" "I[30]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x32" "O[30]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x32" "O[30]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271084 0 0 0.271084 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x32" "A[5]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM1RW512x32" "A[5]" '(
("M1" 0.0366 0.730768 0 0 0.730768 0 0)
("M2" 0.0366 0.1516 19.965 0 0.1516 0 0)
("M3" 0.0366 0.1516 24.1055 0 0.1516 0 0)
("M4" 0.0366 0.1516 28.2457 0 0.1516 0 0)
("M5" 0.0366 0.1516 32.3857 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x32" "A[4]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM1RW512x32" "A[4]" '(
("M1" 0.0366 0.730368 0 0 0.730368 0 0)
("M2" 0.0366 0.1516 19.9541 0 0.1516 0 0)
("M3" 0.0366 0.1516 24.0946 0 0.1516 0 0)
("M4" 0.0366 0.1516 28.2348 0 0.1516 0 0)
("M5" 0.0366 0.1516 32.3747 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x32" "A[3]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM1RW512x32" "A[3]" '(
("M1" 0.0366 0.730668 0 0 0.730668 0 0)
("M2" 0.0366 0.1516 19.9623 0 0.1516 0 0)
("M3" 0.0366 0.1516 24.1028 0 0.1516 0 0)
("M4" 0.0366 0.1516 28.243 0 0.1516 0 0)
("M5" 0.0366 0.1516 32.3829 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x32" "A[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM1RW512x32" "A[2]" '(
("M1" 0.0366 0.730628 0 0 0.730628 0 0)
("M2" 0.0366 0.1516 19.9612 0 0.1516 0 0)
("M3" 0.0366 0.1516 24.1017 0 0.1516 0 0)
("M4" 0.0366 0.1516 28.2419 0 0.1516 0 0)
("M5" 0.0366 0.1516 32.3818 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x32" "A[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW512x32" "A[1]" '(0.6)
defineHierAntennaProp "SRAM1RW512x32" "A[1]" '(
("M1" 0.0366 0.730941 0 0 0.730941 0 0)
("M2" 0.0366 0.1516 19.9697 0 0.1516 0 0)
("M3" 0.0366 0.1516 24.1102 0 0.1516 0 0)
("M4" 0.0366 0.1516 28.2504 0 0.1516 0 0)
("M5" 0.0366 0.1516 32.3904 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x32" "A[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW512x32" "A[0]" '(0.6)
defineHierAntennaProp "SRAM1RW512x32" "A[0]" '(
("M1" 0.0366 0.730668 0 0 0.730668 0 0)
("M2" 0.0366 0.1516 19.9623 0 0.1516 0 0)
("M3" 0.0366 0.1516 24.1028 0 0.1516 0 0)
("M4" 0.0366 0.1516 28.243 0 0.1516 0 0)
("M5" 0.0366 0.1516 32.3829 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x32" "A[6]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW512x32" "A[6]" '(0.6)
defineHierAntennaProp "SRAM1RW512x32" "A[6]" '(
("M1" 0.0366 0.730648 0 0 0.730648 0 0)
("M2" 0.0366 0.1516 19.9617 0 0.1516 0 0)
("M3" 0.0366 0.1516 24.1022 0 0.1516 0 0)
("M4" 0.0366 0.1516 28.2424 0 0.1516 0 0)
("M5" 0.0366 0.1516 32.3824 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x32" "OEB" '(0 0.5178 0.5178 0.5178 0.5178 0.5178 0.5178 0.5178 0.5178 0.5178)
defineDiodeProtection "SRAM1RW512x32" "OEB" '(0.6)
defineHierAntennaProp "SRAM1RW512x32" "OEB" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.5178 2.8813 0.966022 0 2.8813 0 0)
("M3" 0.5178 0.1516 6.53009 0 0.1516 0 0)
("M4" 0.5178 0.1516 6.82242 0 0.1516 0 0)
("M5" 0.5178 0.1516 7.11473 0 0.1516 0 0)
("M6" 0.5178 0 0 0 0 0 0)
("M7" 0.5178 0 0 0 0 0 0)
("M8" 0.5178 0 0 0 0 0 0)
("M9" 0.5178 0 0 0 0 0 0)
("MRDL" 0.5178 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x32" "WEB" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineDiodeProtection "SRAM1RW512x32" "WEB" '(0.6)
defineHierAntennaProp "SRAM1RW512x32" "WEB" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1461 1.56748 1.03833 0 1.56748 0 0)
("M3" 0.1461 0.1516 11.7664 0 0.1516 0 0)
("M4" 0.1461 0.1516 12.8032 0 0.1516 0 0)
("M5" 0.1461 0.1516 13.8399 0 0.1516 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x32" "CSB" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW512x32" "CSB" '(0.6)
defineHierAntennaProp "SRAM1RW512x32" "CSB" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0366 0.437554 1.70239 0 0.437554 0 0)
("M5" 0.0366 0.1516 13.6565 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x32" "O[9]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x32" "O[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271144 0 0 0.271144 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x32" "O[17]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x32" "O[17]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271144 0 0 0.271144 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x32" "O[18]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x32" "O[18]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271144 0 0 0.271144 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x32" "O[21]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x32" "O[21]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271084 0 0 0.271084 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x32" "I[14]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x32" "I[14]" '(0.6)
defineHierAntennaProp "SRAM1RW512x32" "I[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x32" "I[16]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x32" "I[16]" '(0.6)
defineHierAntennaProp "SRAM1RW512x32" "I[16]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x32" "O[24]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x32" "O[24]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271144 0 0 0.271144 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x32" "O[14]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x32" "O[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271144 0 0 0.271144 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x32" "O[15]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x32" "O[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271024 0 0 0.271024 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x32" "O[16]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x32" "O[16]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271084 0 0 0.271084 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x32" "I[12]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x32" "I[12]" '(0.6)
defineHierAntennaProp "SRAM1RW512x32" "I[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x32" "I[13]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x32" "I[13]" '(0.6)
defineHierAntennaProp "SRAM1RW512x32" "I[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28152 1.24827 0 1.28152 0 0)
("M4" 0.021 0.1516 62.2689 0 0.1516 0 0)
("M5" 0.021 0.1516 69.4834 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x32" "I[24]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x32" "I[24]" '(0.6)
defineHierAntennaProp "SRAM1RW512x32" "I[24]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x32" "O[11]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x32" "O[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271144 0 0 0.271144 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x32" "O[12]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x32" "O[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271144 0 0 0.271144 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x32" "O[13]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x32" "O[13]" '(
("M1" 0 0.1536 0 0 0.1536 0 0)
("M2" 0 0.1536 0 0 0.1536 0 0)
("M3" 0 0.272424 0 0 0.272424 0 0)
("M4" 0 0.1536 0 0 0.1536 0 0)
("M5" 0 0.1536 0 0 0.1536 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x32" "O[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x32" "O[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271564 0 0 0.271564 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x32" "O[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x32" "O[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271144 0 0 0.271144 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x32" "I[10]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x32" "I[10]" '(0.6)
defineHierAntennaProp "SRAM1RW512x32" "I[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x32" "I[7]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x32" "I[7]" '(0.6)
defineHierAntennaProp "SRAM1RW512x32" "I[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x32" "O[19]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x32" "O[19]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271324 0 0 0.271324 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x32" "O[26]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x32" "O[26]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271084 0 0 0.271084 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x32" "I[18]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x32" "I[18]" '(0.6)
defineHierAntennaProp "SRAM1RW512x32" "I[18]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x32" "I[25]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x32" "I[25]" '(0.6)
defineHierAntennaProp "SRAM1RW512x32" "I[25]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x32" "I[20]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x32" "I[20]" '(0.6)
defineHierAntennaProp "SRAM1RW512x32" "I[20]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x32" "I[19]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x32" "I[19]" '(0.6)
defineHierAntennaProp "SRAM1RW512x32" "I[19]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x32" "O[25]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x32" "O[25]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271084 0 0 0.271084 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x32" "O[20]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x32" "O[20]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271084 0 0 0.271084 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x32" "I[22]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x32" "I[22]" '(0.6)
defineHierAntennaProp "SRAM1RW512x32" "I[22]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x32" "I[8]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x32" "I[8]" '(0.6)
defineHierAntennaProp "SRAM1RW512x32" "I[8]" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28297 1.24827 0 1.28297 0 0)
("M4" 0.021 0.1516 62.3381 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5525 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x32" "I[23]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x32" "I[23]" '(0.6)
defineHierAntennaProp "SRAM1RW512x32" "I[23]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x32" "O[8]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x32" "O[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271144 0 0 0.271144 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x32" "O[22]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x32" "O[22]" '(
("M1" 0 0.1538 0 0 0.1538 0 0)
("M2" 0 0.1538 0 0 0.1538 0 0)
("M3" 0 0.272984 0 0 0.272984 0 0)
("M4" 0 0.1538 0 0 0.1538 0 0)
("M5" 0 0.1538 0 0 0.1538 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x32" "I[9]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x32" "I[9]" '(0.6)
defineHierAntennaProp "SRAM1RW512x32" "I[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x32" "O[23]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x32" "O[23]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271264 0 0 0.271264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x32" "I[17]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x32" "I[17]" '(0.6)
defineHierAntennaProp "SRAM1RW512x32" "I[17]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x32" "I[15]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x32" "I[15]" '(0.6)
defineHierAntennaProp "SRAM1RW512x32" "I[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x32" "I[21]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x32" "I[21]" '(0.6)
defineHierAntennaProp "SRAM1RW512x32" "I[21]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x32" "I[4]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x32" "I[4]" '(0.6)
defineHierAntennaProp "SRAM1RW512x32" "I[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x32" "O[27]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x32" "O[27]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271084 0 0 0.271084 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x32" "O[28]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x32" "O[28]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271144 0 0 0.271144 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x32" "I[28]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x32" "I[28]" '(0.6)
defineHierAntennaProp "SRAM1RW512x32" "I[28]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x32" "I[29]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x32" "I[29]" '(0.6)
defineHierAntennaProp "SRAM1RW512x32" "I[29]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x32" "O[29]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x32" "O[29]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271264 0 0 0.271264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x32" "I[6]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x32" "I[6]" '(0.6)
defineHierAntennaProp "SRAM1RW512x32" "I[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x32" "O[4]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x32" "O[4]" '(
("M1" 0 0.1536 0 0 0.1536 0 0)
("M2" 0 0.1536 0 0 0.1536 0 0)
("M3" 0 0.272544 0 0 0.272544 0 0)
("M4" 0 0.1536 0 0 0.1536 0 0)
("M5" 0 0.1536 0 0 0.1536 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x32" "O[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x32" "O[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271144 0 0 0.271144 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x32" "I[5]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x32" "I[5]" '(0.6)
defineHierAntennaProp "SRAM1RW512x32" "I[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28152 1.24827 0 1.28152 0 0)
("M4" 0.021 0.1516 62.2689 0 0.1516 0 0)
("M5" 0.021 0.1516 69.4834 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x32" "O[5]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x32" "O[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271144 0 0 0.271144 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x32" "I[27]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x32" "I[27]" '(0.6)
defineHierAntennaProp "SRAM1RW512x32" "I[27]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x32" "O[7]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x32" "O[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.270724 0 0 0.270724 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x32" "O[6]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x32" "O[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271444 0 0 0.271444 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x32" "I[26]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x32" "I[26]" '(0.6)
defineHierAntennaProp "SRAM1RW512x32" "I[26]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x32" "VSS" '(0 0 0 0 2.745 2.745 2.745 2.745 2.745 2.745)
defineDiodeProtection "SRAM1RW512x32" "VSS" '(0 0 0 0 1609.666 1609.666 1609.666 1609.666 1609.666 1609.666)
defineHierAntennaProp "SRAM1RW512x32" "VSS" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 2.745 16795.9 112.165 0 16795.9 0 0)
("M6" 2.745 0 0 0 0 0 0)
("M7" 2.745 0 0 0 0 0 0)
("M8" 2.745 0 0 0 0 0 0)
("M9" 2.745 0 0 0 0 0 0)
("MRDL" 2.745 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x32" "A[7]" '(0 0 0 0.0732 0.0732 0.0732 0.0732 0.0732 0.0732 0.0732)
defineDiodeProtection "SRAM1RW512x32" "A[7]" '(0.6)
defineHierAntennaProp "SRAM1RW512x32" "A[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0732 12.2811 3.14056 0 12.2811 0 0)
("M5" 0.0732 0.1516 170.904 0 0.1516 0 0)
("M6" 0.0732 0 0 0 0 0 0)
("M7" 0.0732 0 0 0 0 0 0)
("M8" 0.0732 0 0 0 0 0 0)
("M9" 0.0732 0 0 0 0 0 0)
("MRDL" 0.0732 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x32" "A[8]" '(0 0 0 0.0732 0.0732 0.0732 0.0732 0.0732 0.0732 0.0732)
defineDiodeProtection "SRAM1RW512x32" "A[8]" '(0.6)
defineHierAntennaProp "SRAM1RW512x32" "A[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0732 12.2804 2.1083 0 12.2804 0 0)
("M5" 0.0732 0.1516 169.862 0 0.1516 0 0)
("M6" 0.0732 0 0 0 0 0 0)
("M7" 0.0732 0 0 0 0 0 0)
("M8" 0.0732 0 0 0 0 0 0)
("M9" 0.0732 0 0 0 0 0 0)
("MRDL" 0.0732 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x32" "CE" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineDiodeProtection "SRAM1RW512x32" "CE" '(0.6)
defineHierAntennaProp "SRAM1RW512x32" "CE" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0342 0.281302 3.70059 0 0.281302 0 0)
("M5" 0.0342 0.1516 11.925 0 0.1516 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x32" "O[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x32" "O[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.271144 0 0 0.271144 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x32" "I[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x32" "I[0]" '(0.6)
defineHierAntennaProp "SRAM1RW512x32" "I[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x32" "I[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x32" "I[1]" '(0.6)
defineHierAntennaProp "SRAM1RW512x32" "I[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28188 1.24827 0 1.28188 0 0)
("M4" 0.021 0.1516 62.2861 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5005 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[17]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW512x128" "I[17]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[16]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[16]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[15]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[16]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW512x128" "I[16]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[17]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[17]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[12]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[13]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[13]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW512x128" "I[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[14]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW512x128" "I[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[14]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[15]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW512x128" "I[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[10]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[12]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[12]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[11]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[11]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[11]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[9]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[8]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[9]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[9]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[10]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[10]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[25]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[25]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[26]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[26]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[25]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[25]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[25]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[26]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[26]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[26]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[24]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[24]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[24]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[24]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[24]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[23]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[23]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[23]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[23]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[23]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[22]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[22]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[20]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[20]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[20]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[22]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[22]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[22]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[21]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[21]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[21]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[21]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[21]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[20]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[20]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[18]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[18]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[19]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[19]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[19]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[19]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[19]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[18]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[18]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[18]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[46]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[46]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[46]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[46]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[46]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[48]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[48]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[64]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[64]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[64]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[64]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[64]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[62]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[62]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[62]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[62]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[62]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[63]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[63]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[63]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[63]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[63]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[61]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[61]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[59]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[59]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[59]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[60]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[60]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[60]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[58]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[58]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[58]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[58]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[58]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[60]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[60]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[61]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[61]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[61]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[59]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[59]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[55]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[55]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[57]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[57]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[57]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[56]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[56]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[56]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[56]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[56]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[57]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[57]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[73]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[73]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[73]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[73]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[73]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[72]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[72]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[71]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[71]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[72]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[72]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[72]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[70]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[70]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[71]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[71]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[71]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[69]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[69]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[70]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[70]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[70]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[68]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[68]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[68]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[68]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[68]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[69]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[69]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[69]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[67]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[67]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[65]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[65]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[66]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[66]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[67]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[67]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[67]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[66]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[66]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[66]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[65]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[65]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[65]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "A[8]" '(0 0 0 0.0732 0.0732 0.0732 0.0732 0.0732 0.0732 0.0732)
defineDiodeProtection "SRAM1RW512x128" "A[8]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "A[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0732 43.8522 1.99528 0 43.8522 0 0)
("M5" 0.0732 0.1516 601.03 0 0.1516 0 0)
("M6" 0.0732 0 0 0 0 0 0)
("M7" 0.0732 0 0 0 0 0 0)
("M8" 0.0732 0 0 0 0 0 0)
("M9" 0.0732 0 0 0 0 0 0)
("MRDL" 0.0732 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "CE" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineDiodeProtection "SRAM1RW512x128" "CE" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "CE" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0342 0.37546 3.80246 0 0.37546 0 0)
("M5" 0.0342 0.1516 14.7799 0 0.1516 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[48]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[48]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[48]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[81]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[81]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[81]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[81]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[81]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[80]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[80]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[79]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[79]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[79]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[79]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[79]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[78]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[78]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[78]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[77]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[77]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[80]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[80]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[80]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[77]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[77]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[77]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[78]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[78]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[75]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[75]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[75]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[75]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[75]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[74]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[74]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[76]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[76]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[76]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[76]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[76]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[74]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[74]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[74]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[8]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[8]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[7]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[7]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[7]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[6]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[6]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[6]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[5]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[5]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[5]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[1]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1514 62.3746 0 0.1514 0 0)
("M5" 0.021 0.1514 69.5795 0 0.1514 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[3]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[4]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[4]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[4]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[0]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "OEB" '(0 2.0154 2.0154 2.0154 2.0154 2.0154 2.0154 2.0154 2.0154 2.0154)
defineDiodeProtection "SRAM1RW512x128" "OEB" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "OEB" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 2.0154 10.7628 0.966025 0 10.7628 0 0)
("M3" 2.0154 0.1516 6.30588 0 0.1516 0 0)
("M4" 2.0154 0.1516 6.38068 0 0.1516 0 0)
("M5" 2.0154 0.1516 6.45547 0 0.1516 0 0)
("M6" 2.0154 0 0 0 0 0 0)
("M7" 2.0154 0 0 0 0 0 0)
("M8" 2.0154 0 0 0 0 0 0)
("M9" 2.0154 0 0 0 0 0 0)
("MRDL" 2.0154 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "WEB" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineDiodeProtection "SRAM1RW512x128" "WEB" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "WEB" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1461 1.6432 1.03834 0 1.6432 0 0)
("M3" 0.1461 0.1516 12.2846 0 0.1516 0 0)
("M4" 0.1461 0.1516 13.3214 0 0.1516 0 0)
("M5" 0.1461 0.1516 14.3581 0 0.1516 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "A[7]" '(0 0 0 0.0732 0.0732 0.0732 0.0732 0.0732 0.0732 0.0732)
defineDiodeProtection "SRAM1RW512x128" "A[7]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "A[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0732 43.8363 2.92212 0 43.8363 0 0)
("M5" 0.0732 0.1516 601.739 0 0.1516 0 0)
("M6" 0.0732 0 0 0 0 0 0)
("M7" 0.0732 0 0 0 0 0 0)
("M8" 0.0732 0 0 0 0 0 0)
("M9" 0.0732 0 0 0 0 0 0)
("MRDL" 0.0732 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[124]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[124]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[123]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[123]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[123]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[122]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[122]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[122]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[122]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[122]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[120]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[120]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[121]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[121]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[121]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[121]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[121]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[119]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[119]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[119]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[119]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[119]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[120]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[120]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[120]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[118]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[118]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[118]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[118]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[118]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "A[5]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW512x128" "A[5]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "A[5]" '(
("M1" 0.0366 0.703568 0 0 0.703568 0 0)
("M2" 0.0366 0.1516 19.2219 0 0.1516 0 0)
("M3" 0.0366 0.1516 23.3624 0 0.1516 0 0)
("M4" 0.0366 0.1516 27.5027 0 0.1516 0 0)
("M5" 0.0366 0.1516 31.6427 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "A[6]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW512x128" "A[6]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "A[6]" '(
("M1" 0.0366 0.703568 0 0 0.703568 0 0)
("M2" 0.0366 0.1516 19.2219 0 0.1516 0 0)
("M3" 0.0366 0.1516 23.3624 0 0.1516 0 0)
("M4" 0.0366 0.1516 27.5027 0 0.1516 0 0)
("M5" 0.0366 0.1516 31.6427 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[2]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "CSB" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW512x128" "CSB" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "CSB" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0366 0.500569 1.92429 0 0.500569 0 0)
("M5" 0.0366 0.1516 15.6 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[127]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[127]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[127]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[127]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[127]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "VSS" '(0 0 0 0 2.745 2.745 2.745 2.745 2.745 2.745)
defineDiodeProtection "SRAM1RW512x128" "VSS" '(0 0 0 0 6449.748 6449.748 6449.748 6449.748 6449.748 6449.748)
defineHierAntennaProp "SRAM1RW512x128" "VSS" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 2.745 72514.6 189.496 0 72514.6 0 0)
("M6" 2.745 0 0 0 0 0 0)
("M7" 2.745 0 0 0 0 0 0)
("M8" 2.745 0 0 0 0 0 0)
("M9" 2.745 0 0 0 0 0 0)
("MRDL" 2.745 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[27]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[27]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "A[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW512x128" "A[2]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "A[2]" '(
("M1" 0.0366 0.703568 0 0 0.703568 0 0)
("M2" 0.0366 0.1516 19.2219 0 0.1516 0 0)
("M3" 0.0366 0.1516 23.3624 0 0.1516 0 0)
("M4" 0.0366 0.1516 27.5027 0 0.1516 0 0)
("M5" 0.0366 0.1516 31.6427 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "A[3]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW512x128" "A[3]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "A[3]" '(
("M1" 0.0366 0.703568 0 0 0.703568 0 0)
("M2" 0.0366 0.1516 19.2219 0 0.1516 0 0)
("M3" 0.0366 0.1516 23.3624 0 0.1516 0 0)
("M4" 0.0366 0.1516 27.5027 0 0.1516 0 0)
("M5" 0.0366 0.1516 31.6427 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "A[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW512x128" "A[1]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "A[1]" '(
("M1" 0.0366 0.703568 0 0 0.703568 0 0)
("M2" 0.0366 0.1516 19.2219 0 0.1516 0 0)
("M3" 0.0366 0.1516 23.3624 0 0.1516 0 0)
("M4" 0.0366 0.1516 27.5027 0 0.1516 0 0)
("M5" 0.0366 0.1516 31.6427 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "A[4]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW512x128" "A[4]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "A[4]" '(
("M1" 0.0366 0.703568 0 0 0.703568 0 0)
("M2" 0.0366 0.1516 19.2219 0 0.1516 0 0)
("M3" 0.0366 0.1516 23.3624 0 0.1516 0 0)
("M4" 0.0366 0.1516 27.5027 0 0.1516 0 0)
("M5" 0.0366 0.1516 31.6427 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "A[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW512x128" "A[0]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "A[0]" '(
("M1" 0.0366 0.703568 0 0 0.703568 0 0)
("M2" 0.0366 0.1516 19.2219 0 0.1516 0 0)
("M3" 0.0366 0.1516 23.3624 0 0.1516 0 0)
("M4" 0.0366 0.1516 27.5027 0 0.1516 0 0)
("M5" 0.0366 0.1516 31.6427 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "VDD" '(0 0 0 0 1.5408 1.5408 1.5408 1.5408 1.5408 1.5408)
defineDiodeProtection "SRAM1RW512x128" "VDD" '(0 0 0 0 4747.311 4747.311 4747.311 4747.311 4747.311 4747.311)
defineHierAntennaProp "SRAM1RW512x128" "VDD" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 1.5408 72514.4 28.783 0 72514.4 0 0)
("M6" 1.5408 0 0 0 0 0 0)
("M7" 1.5408 0 0 0 0 0 0)
("M8" 1.5408 0 0 0 0 0 0)
("M9" 1.5408 0 0 0 0 0 0)
("MRDL" 1.5408 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[37]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[37]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[37]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[36]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[36]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[35]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[35]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[35]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[35]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[35]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[33]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[33]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[32]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[32]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[32]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[32]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[32]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[34]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[34]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[33]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[33]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[33]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[34]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[34]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[34]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[30]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[30]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[30]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[29]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[29]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[30]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[30]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[31]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[31]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[31]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[31]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[31]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[28]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[28]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[28]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[27]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[27]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[27]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[28]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[28]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[29]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[29]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[29]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[44]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[44]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[45]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[45]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[45]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[45]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[45]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[44]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[44]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[44]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[43]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[43]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[43]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[43]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[43]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[42]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[42]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[40]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[40]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[42]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[42]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[42]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[41]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[41]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[41]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[41]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[41]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[40]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[40]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[40]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[39]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[39]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[39]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[39]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[39]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[38]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[38]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[38]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[37]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[37]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[38]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[38]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[36]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[36]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[36]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[55]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[55]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[55]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[54]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[54]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[53]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[53]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[53]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[52]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[52]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[52]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[53]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[53]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[54]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[54]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[54]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[52]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[52]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[51]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[51]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[51]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[51]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[51]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[50]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[50]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[50]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[50]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[50]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[49]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[49]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[49]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[49]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[49]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[47]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[47]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[47]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[47]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[47]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1514 62.3746 0 0.1514 0 0)
("M5" 0.021 0.1514 69.5795 0 0.1514 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[89]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[89]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[87]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[87]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[87]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[89]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[89]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[89]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[88]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[88]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[87]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[87]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[88]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[88]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[88]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[86]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[86]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[86]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[86]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[86]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[85]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[85]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[85]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[83]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[83]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[84]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[84]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[85]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[85]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[84]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[84]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[84]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[83]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[83]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[83]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[82]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[82]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[82]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[82]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[82]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[97]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[97]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[99]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[99]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[99]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[99]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[99]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[98]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[98]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[97]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[97]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[97]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[96]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[96]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[94]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[94]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[95]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[95]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[95]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[95]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[95]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[96]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[96]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[96]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[93]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[93]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[94]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[94]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[94]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[93]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[93]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[93]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1514 62.3746 0 0.1514 0 0)
("M5" 0.021 0.1514 69.5795 0 0.1514 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[90]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[90]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[92]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[92]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[92]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[92]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[92]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[91]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[91]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[91]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[91]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[91]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[90]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[90]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[90]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[108]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[108]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[108]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[106]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[106]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[107]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[107]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[107]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[106]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[106]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[106]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[107]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[107]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[105]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[105]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[105]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[104]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[104]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[104]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[104]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[104]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[105]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[105]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[103]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[103]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[102]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[102]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[103]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[103]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[103]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[101]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[101]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[101]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[101]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[101]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[100]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[100]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[102]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[102]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[102]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[100]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[100]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[100]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[98]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[98]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[98]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[116]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[116]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[116]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[116]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[116]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[115]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[115]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[115]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[115]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[115]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[117]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[117]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[117]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[117]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[117]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[113]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[113]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[112]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[112]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[112]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[114]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[114]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[114]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[112]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[112]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[113]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[113]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[113]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[114]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[114]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[110]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[110]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[109]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[109]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[109]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[109]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[109]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[111]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[111]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[111]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[111]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[111]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[110]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[110]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[110]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[108]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[108]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[126]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[126]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[126]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[126]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[126]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[125]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[125]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW512x128" "O[123]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW512x128" "O[123]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[125]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[125]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[125]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW512x128" "I[124]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW512x128" "I[124]" '(0.6)
defineHierAntennaProp "SRAM1RW512x128" "I[124]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW1024x8" "I[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW1024x8" "I[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW1024x8" "O[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW1024x8" "O[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277608 0 0 0.277608 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW1024x8" "WEB" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineHierAntennaProp "SRAM1RW1024x8" "WEB" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1461 1.58404 1.03834 0 1.58404 0 0)
("M3" 0.1461 0.1516 11.8797 0 0.1516 0 0)
("M4" 0.1461 0.1516 12.9165 0 0.1516 0 0)
("M5" 0.1461 0.1516 13.9532 0 0.1516 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW1024x8" "CE" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineHierAntennaProp "SRAM1RW1024x8" "CE" '(
("M1" 0 0.1498 0 0 0.1498 0 0)
("M2" 0 0.1498 0 0 0.1498 0 0)
("M3" 0 0.1498 0 0 0.1498 0 0)
("M4" 0.0342 0.3148 3.90093 0 0.3148 0 0)
("M5" 0.0342 0.1498 13.1047 0 0.1498 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW1024x8" "I[4]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW1024x8" "I[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW1024x8" "I[7]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW1024x8" "I[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW1024x8" "O[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW1024x8" "O[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW1024x8" "O[5]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW1024x8" "O[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW1024x8" "O[4]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW1024x8" "O[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW1024x8" "I[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM1RW1024x8" "I[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW1024x8" "O[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW1024x8" "O[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW1024x8" "O[7]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW1024x8" "O[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW1024x8" "CSB" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM1RW1024x8" "CSB" '(
("M1" 0 0.1498 0 0 0.1498 0 0)
("M2" 0 0.1498 0 0 0.1498 0 0)
("M3" 0 0.1498 0 0 0.1498 0 0)
("M4" 0.0366 0.437869 1.94146 0 0.437869 0 0)
("M5" 0.0366 0.1498 13.9042 0 0.1498 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW1024x8" "A[6]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM1RW1024x8" "A[6]" '(
("M1" 0.0366 0.74594 0 0 0.74594 0 0)
("M2" 0.0366 0.1504 20.3795 0 0.1504 0 0)
("M3" 0.0366 0.1504 24.4872 0 0.1504 0 0)
("M4" 0.0366 0.1504 28.5946 0 0.1504 0 0)
("M5" 0.0366 0.1504 32.7017 0 0.1504 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW1024x8" "A[5]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW1024x8" "A[5]" '(0.6)
defineHierAntennaProp "SRAM1RW1024x8" "A[5]" '(
("M1" 0.0366 0.745908 0 0 0.745908 0 0)
("M2" 0.0366 0.1504 20.3786 0 0.1504 0 0)
("M3" 0.0366 0.1504 24.4863 0 0.1504 0 0)
("M4" 0.0366 0.1504 28.5937 0 0.1504 0 0)
("M5" 0.0366 0.1504 32.7008 0 0.1504 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW1024x8" "A[4]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW1024x8" "A[4]" '(0.6)
defineHierAntennaProp "SRAM1RW1024x8" "A[4]" '(
("M1" 0.0366 0.745908 0 0 0.745908 0 0)
("M2" 0.0366 0.1504 20.3786 0 0.1504 0 0)
("M3" 0.0366 0.1504 24.4863 0 0.1504 0 0)
("M4" 0.0366 0.1504 28.5937 0 0.1504 0 0)
("M5" 0.0366 0.1504 32.7008 0 0.1504 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW1024x8" "A[3]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW1024x8" "A[3]" '(0.6)
defineHierAntennaProp "SRAM1RW1024x8" "A[3]" '(
("M1" 0.0366 0.745908 0 0 0.745908 0 0)
("M2" 0.0366 0.1504 20.3786 0 0.1504 0 0)
("M3" 0.0366 0.1504 24.4863 0 0.1504 0 0)
("M4" 0.0366 0.1504 28.5937 0 0.1504 0 0)
("M5" 0.0366 0.1504 32.7008 0 0.1504 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW1024x8" "A[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW1024x8" "A[0]" '(0.6)
defineHierAntennaProp "SRAM1RW1024x8" "A[0]" '(
("M1" 0.0366 0.745908 0 0 0.745908 0 0)
("M2" 0.0366 0.1504 20.3786 0 0.1504 0 0)
("M3" 0.0366 0.1504 24.4863 0 0.1504 0 0)
("M4" 0.0366 0.1504 28.5937 0 0.1504 0 0)
("M5" 0.0366 0.1504 32.7008 0 0.1504 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW1024x8" "A[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW1024x8" "A[1]" '(0.6)
defineHierAntennaProp "SRAM1RW1024x8" "A[1]" '(
("M1" 0.0366 0.745908 0 0 0.745908 0 0)
("M2" 0.0366 0.1504 20.3786 0 0.1504 0 0)
("M3" 0.0366 0.1504 24.4863 0 0.1504 0 0)
("M4" 0.0366 0.1504 28.5937 0 0.1504 0 0)
("M5" 0.0366 0.1504 32.7008 0 0.1504 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW1024x8" "A[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW1024x8" "A[2]" '(0.6)
defineHierAntennaProp "SRAM1RW1024x8" "A[2]" '(
("M1" 0.0366 0.745908 0 0 0.745908 0 0)
("M2" 0.0366 0.1504 20.3786 0 0.1504 0 0)
("M3" 0.0366 0.1504 24.4863 0 0.1504 0 0)
("M4" 0.0366 0.1504 28.5937 0 0.1504 0 0)
("M5" 0.0366 0.1504 32.7008 0 0.1504 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW1024x8" "A[9]" '(0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW1024x8" "A[9]" '(0.6)
defineHierAntennaProp "SRAM1RW1024x8" "A[9]" '(
("M1" 0 0.80259 0 0 0.80259 0 0)
("M2" 0.0366 0.19804 1.58921 0 0.19804 0 0)
("M3" 0.0366 0.1504 6.99967 0 0.1504 0 0)
("M4" 0.0366 0.1504 11.1082 0 0.1504 0 0)
("M5" 0.0366 0.1504 15.2165 0 0.1504 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW1024x8" "A[8]" '(0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW1024x8" "A[8]" '(0.6)
defineHierAntennaProp "SRAM1RW1024x8" "A[8]" '(
("M1" 0 0.1504 0 0 0.1504 0 0)
("M2" 0.0366 0.42598 1.58925 0 0.42598 0 0)
("M3" 0.0366 0.1504 13.2272 0 0.1504 0 0)
("M4" 0.0366 0.1504 17.3353 0 0.1504 0 0)
("M5" 0.0366 0.1504 21.4432 0 0.1504 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW1024x8" "A[7]" '(0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM1RW1024x8" "A[7]" '(0.6)
defineHierAntennaProp "SRAM1RW1024x8" "A[7]" '(
("M1" 0 0.1504 0 0 0.1504 0 0)
("M2" 0 0.1504 0 0 0.1504 0 0)
("M3" 0.0366 0.69256 11.898 0 0.69256 0 0)
("M4" 0.0366 0.1504 30.8183 0 0.1504 0 0)
("M5" 0.0366 0.1504 34.9253 0 0.1504 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW1024x8" "I[5]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW1024x8" "I[5]" '(0.6)
defineHierAntennaProp "SRAM1RW1024x8" "I[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW1024x8" "I[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW1024x8" "I[1]" '(0.6)
defineHierAntennaProp "SRAM1RW1024x8" "I[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW1024x8" "VSS" '(0 0 0 0 2.745 2.745 2.745 2.745 2.745 2.745)
defineDiodeProtection "SRAM1RW1024x8" "VSS" '(0 0 0 0 837.9736 837.9736 837.9736 837.9736 837.9736 837.9736)
defineHierAntennaProp "SRAM1RW1024x8" "VSS" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 2.745 8463.03 110.57 0 8463.03 0 0)
("M6" 2.745 0 0 0 0 0 0)
("M7" 2.745 0 0 0 0 0 0)
("M8" 2.745 0 0 0 0 0 0)
("M9" 2.745 0 0 0 0 0 0)
("MRDL" 2.745 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW1024x8" "I[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW1024x8" "I[0]" '(0.6)
defineHierAntennaProp "SRAM1RW1024x8" "I[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW1024x8" "OEB" '(0 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434)
defineDiodeProtection "SRAM1RW1024x8" "OEB" '(0.6)
defineHierAntennaProp "SRAM1RW1024x8" "OEB" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1434 0.91174 0.966015 0 0.91174 0 0)
("M3" 0.1434 0.1516 7.32355 0 0.1516 0 0)
("M4" 0.1434 0.1516 8.38018 0 0.1516 0 0)
("M5" 0.1434 0.1516 9.43675 0 0.1516 0 0)
("M6" 0.1434 0 0 0 0 0 0)
("M7" 0.1434 0 0 0 0 0 0)
("M8" 0.1434 0 0 0 0 0 0)
("M9" 0.1434 0 0 0 0 0 0)
("MRDL" 0.1434 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW1024x8" "O[6]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW1024x8" "O[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW1024x8" "I[6]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM1RW1024x8" "I[6]" '(0.6)
defineHierAntennaProp "SRAM1RW1024x8" "I[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM1RW1024x8" "O[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM1RW1024x8" "O[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM1RW1024x8" "VDD" '(0 0 0 0 1.5408 1.5408 1.5408 1.5408 1.5408 1.5408)
defineDiodeProtection "SRAM1RW1024x8" "VDD" '(0 0 0 0 647.8152 647.8152 647.8152 647.8152 647.8152 647.8152)
defineHierAntennaProp "SRAM1RW1024x8" "VDD" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 1.5408 8463.02 28.9898 0 8463.02 0 0)
("M6" 1.5408 0 0 0 0 0 0)
("M7" 1.5408 0 0 0 0 0 0)
("M8" 1.5408 0 0 0 0 0 0)
("M9" 1.5408 0 0 0 0 0 0)
("MRDL" 1.5408 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x4" "I1[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW16x4" "I1[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28128 1.24827 0 1.28128 0 0)
("M4" 0.021 0.1516 62.2575 0 0.1516 0 0)
("M5" 0.021 0.1516 69.472 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x4" "CE2" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineHierAntennaProp "SRAM2RW16x4" "CE2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0342 0.28378 4.85233 0 0.28378 0 0)
("M5" 0.0342 0.1516 13.1491 0 0.1516 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x4" "CSB2" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM2RW16x4" "CSB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0366 0.3946 1.96773 0 0.3946 0 0)
("M5" 0.0366 0.1516 12.7483 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x4" "A2[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM2RW16x4" "A2[1]" '(
("M1" 0.0366 0.961668 0 0 0.961668 0 0)
("M2" 0.0366 0.1516 26.2734 0 0.1516 0 0)
("M3" 0.0366 0.1516 30.4134 0 0.1516 0 0)
("M4" 0.0366 0.1516 34.5532 0 0.1516 0 0)
("M5" 0.0366 0.1516 38.6927 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x4" "A2[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM2RW16x4" "A2[2]" '(
("M1" 0.0366 0.961668 0 0 0.961668 0 0)
("M2" 0.0366 0.1516 26.2734 0 0.1516 0 0)
("M3" 0.0366 0.1516 30.4134 0 0.1516 0 0)
("M4" 0.0366 0.1516 34.5532 0 0.1516 0 0)
("M5" 0.0366 0.1516 38.6927 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x4" "A2[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM2RW16x4" "A2[0]" '(
("M1" 0.0366 0.961668 0 0 0.961668 0 0)
("M2" 0.0366 0.1516 26.2734 0 0.1516 0 0)
("M3" 0.0366 0.1516 30.4134 0 0.1516 0 0)
("M4" 0.0366 0.1516 34.5532 0 0.1516 0 0)
("M5" 0.0366 0.1516 38.6927 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x4" "A2[3]" '(0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW16x4" "A2[3]" '(
("M1" 0.021 0.96757 0 0 0.96757 0 0)
("M2" 0.021 0.1516 46.0717 0 0.1516 0 0)
("M3" 0.021 0.1516 53.2873 0 0.1516 0 0)
("M4" 0.021 0.1516 60.5023 0 0.1516 0 0)
("M5" 0.021 0.1516 67.7169 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x4" "A1[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM2RW16x4" "A1[1]" '(
("M1" 0.0366 0.970068 0 0 0.970068 0 0)
("M2" 0.0366 0.1516 26.5028 0 0.1516 0 0)
("M3" 0.0366 0.1516 30.6429 0 0.1516 0 0)
("M4" 0.0366 0.1516 34.7827 0 0.1516 0 0)
("M5" 0.0366 0.1516 38.9222 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x4" "A1[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM2RW16x4" "A1[2]" '(
("M1" 0.0366 0.970068 0 0 0.970068 0 0)
("M2" 0.0366 0.1516 26.5028 0 0.1516 0 0)
("M3" 0.0366 0.1516 30.6429 0 0.1516 0 0)
("M4" 0.0366 0.1516 34.7827 0 0.1516 0 0)
("M5" 0.0366 0.1516 38.9222 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x4" "A1[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM2RW16x4" "A1[0]" '(
("M1" 0.0366 0.970068 0 0 0.970068 0 0)
("M2" 0.0366 0.1516 26.5028 0 0.1516 0 0)
("M3" 0.0366 0.1516 30.6429 0 0.1516 0 0)
("M4" 0.0366 0.1516 34.7827 0 0.1516 0 0)
("M5" 0.0366 0.1516 38.9222 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x4" "CSB1" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM2RW16x4" "CSB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0366 0.40516 1.96489 0 0.40516 0 0)
("M5" 0.0366 0.1516 13.034 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x4" "CE1" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineHierAntennaProp "SRAM2RW16x4" "CE1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0342 0.30634 4.24673 0 0.30634 0 0)
("M5" 0.0342 0.1516 13.2032 0 0.1516 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x4" "A1[3]" '(0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x4" "A1[3]" '(0.6)
defineHierAntennaProp "SRAM2RW16x4" "A1[3]" '(
("M1" 0.021 0.97597 0 0 0.97597 0 0)
("M2" 0.021 0.1516 46.4717 0 0.1516 0 0)
("M3" 0.021 0.1516 53.6872 0 0.1516 0 0)
("M4" 0.021 0.1516 60.9022 0 0.1516 0 0)
("M5" 0.021 0.1516 68.1168 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x4" "O1[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x4" "O1[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.269224 0 0 0.269224 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x4" "OEB2" '(0 0.081 0.081 0.081 0.081 0.081 0.081 0.081 0.081 0.081)
defineDiodeProtection "SRAM2RW16x4" "OEB2" '(0.6)
defineHierAntennaProp "SRAM2RW16x4" "OEB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.081 0.59457 0.966009 0 0.59457 0 0)
("M3" 0.081 0.1516 8.30584 0 0.1516 0 0)
("M4" 0.081 0.1516 10.1768 0 0.1516 0 0)
("M5" 0.081 0.1516 12.0476 0 0.1516 0 0)
("M6" 0.081 0 0 0 0 0 0)
("M7" 0.081 0 0 0 0 0 0)
("M8" 0.081 0 0 0 0 0 0)
("M9" 0.081 0 0 0 0 0 0)
("MRDL" 0.081 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x4" "OEB1" '(0 0.081 0.081 0.081 0.081 0.081 0.081 0.081 0.081 0.081)
defineDiodeProtection "SRAM2RW16x4" "OEB1" '(0.6)
defineHierAntennaProp "SRAM2RW16x4" "OEB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.081 0.604505 0.966009 0 0.604505 0 0)
("M3" 0.081 0.1516 8.42848 0 0.1516 0 0)
("M4" 0.081 0.1516 10.2994 0 0.1516 0 0)
("M5" 0.081 0.1516 12.1702 0 0.1516 0 0)
("M6" 0.081 0 0 0 0 0 0)
("M7" 0.081 0 0 0 0 0 0)
("M8" 0.081 0 0 0 0 0 0)
("M9" 0.081 0 0 0 0 0 0)
("MRDL" 0.081 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x4" "WEB1" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineDiodeProtection "SRAM2RW16x4" "WEB1" '(0.6)
defineHierAntennaProp "SRAM2RW16x4" "WEB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1461 1.5667 1.03833 0 1.5667 0 0)
("M3" 0.1461 0.1516 11.761 0 0.1516 0 0)
("M4" 0.1461 0.1516 12.7978 0 0.1516 0 0)
("M5" 0.1461 0.1516 13.8346 0 0.1516 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x4" "WEB2" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineDiodeProtection "SRAM2RW16x4" "WEB2" '(0.6)
defineHierAntennaProp "SRAM2RW16x4" "WEB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1461 1.55662 1.03834 0 1.55662 0 0)
("M3" 0.1461 0.1516 11.692 0 0.1516 0 0)
("M4" 0.1461 0.1516 12.7289 0 0.1516 0 0)
("M5" 0.1461 0.1516 13.7656 0 0.1516 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x4" "O2[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x4" "O2[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.270888 0 0 0.270888 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x4" "I2[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x4" "I2[1]" '(0.6)
defineHierAntennaProp "SRAM2RW16x4" "I2[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28128 1.24827 0 1.28128 0 0)
("M4" 0.021 0.1516 62.2575 0 0.1516 0 0)
("M5" 0.021 0.1516 69.472 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x4" "I2[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x4" "I2[2]" '(0.6)
defineHierAntennaProp "SRAM2RW16x4" "I2[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28128 1.24827 0 1.28128 0 0)
("M4" 0.021 0.1516 62.2575 0 0.1516 0 0)
("M5" 0.021 0.1516 69.472 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x4" "I2[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x4" "I2[0]" '(0.6)
defineHierAntennaProp "SRAM2RW16x4" "I2[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28128 1.24827 0 1.28128 0 0)
("M4" 0.021 0.1516 62.2575 0 0.1516 0 0)
("M5" 0.021 0.1516 69.472 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x4" "I1[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x4" "I1[2]" '(0.6)
defineHierAntennaProp "SRAM2RW16x4" "I1[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28128 1.24827 0 1.28128 0 0)
("M4" 0.021 0.1516 62.2575 0 0.1516 0 0)
("M5" 0.021 0.1516 69.472 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x4" "O2[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x4" "O2[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.270888 0 0 0.270888 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x4" "O1[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x4" "O1[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.270888 0 0 0.270888 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x4" "O1[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x4" "O1[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.270888 0 0 0.270888 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x4" "I1[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x4" "I1[3]" '(0.6)
defineHierAntennaProp "SRAM2RW16x4" "I1[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28128 1.24827 0 1.28128 0 0)
("M4" 0.021 0.1516 62.2575 0 0.1516 0 0)
("M5" 0.021 0.1516 69.472 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x4" "I1[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x4" "I1[1]" '(0.6)
defineHierAntennaProp "SRAM2RW16x4" "I1[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28128 1.24827 0 1.28128 0 0)
("M4" 0.021 0.1516 62.2575 0 0.1516 0 0)
("M5" 0.021 0.1516 69.472 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x4" "O1[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x4" "O1[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.270888 0 0 0.270888 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x4" "O2[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x4" "O2[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.270888 0 0 0.270888 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x4" "I2[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x4" "I2[3]" '(0.6)
defineHierAntennaProp "SRAM2RW16x4" "I2[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28128 1.24827 0 1.28128 0 0)
("M4" 0.021 0.1516 62.2575 0 0.1516 0 0)
("M5" 0.021 0.1516 69.472 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x4" "O2[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x4" "O2[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.270888 0 0 0.270888 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x4" "VDD" '(0 0 0 0 3.0816 3.0816 3.0816 3.0816 3.0816 3.0816)
defineDiodeProtection "SRAM2RW16x4" "VDD" '(0 0 0 0 64.60491 64.60491 64.60491 64.60491 64.60491 64.60491)
defineHierAntennaProp "SRAM2RW16x4" "VDD" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 3.0816 741.691 29.0976 0 741.691 0 0)
("M6" 3.0816 0 0 0 0 0 0)
("M7" 3.0816 0 0 0 0 0 0)
("M8" 3.0816 0 0 0 0 0 0)
("M9" 3.0816 0 0 0 0 0 0)
("MRDL" 3.0816 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x4" "VSS" '(0 0 0 0 5.49 5.49 5.49 5.49 5.49 5.49)
defineDiodeProtection "SRAM2RW16x4" "VSS" '(0 0 0 0 49.17457 49.17457 49.17457 49.17457 49.17457 49.17457)
defineHierAntennaProp "SRAM2RW16x4" "VSS" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 5.49 741.736 86.3142 0 741.736 0 0)
("M6" 5.49 0 0 0 0 0 0)
("M7" 5.49 0 0 0 0 0 0)
("M8" 5.49 0 0 0 0 0 0)
("M9" 5.49 0 0 0 0 0 0)
("MRDL" 5.49 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x8" "OEB1" '(0 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434)
defineHierAntennaProp "SRAM2RW16x8" "OEB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1434 0.910072 0.966015 0 0.910072 0 0)
("M3" 0.1434 0.1516 7.31192 0 0.1516 0 0)
("M4" 0.1434 0.1516 8.36855 0 0.1516 0 0)
("M5" 0.1434 0.1516 9.42511 0 0.1516 0 0)
("M6" 0.1434 0 0 0 0 0 0)
("M7" 0.1434 0 0 0 0 0 0)
("M8" 0.1434 0 0 0 0 0 0)
("M9" 0.1434 0 0 0 0 0 0)
("MRDL" 0.1434 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x8" "OEB2" '(0 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434)
defineHierAntennaProp "SRAM2RW16x8" "OEB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1434 0.904252 0.966015 0 0.904252 0 0)
("M3" 0.1434 0.1516 7.27134 0 0.1516 0 0)
("M4" 0.1434 0.1516 8.32797 0 0.1516 0 0)
("M5" 0.1434 0.1516 9.38454 0 0.1516 0 0)
("M6" 0.1434 0 0 0 0 0 0)
("M7" 0.1434 0 0 0 0 0 0)
("M8" 0.1434 0 0 0 0 0 0)
("M9" 0.1434 0 0 0 0 0 0)
("MRDL" 0.1434 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x8" "O2[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x8" "O2[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.25894 0 0 0.25894 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x8" "O2[7]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x8" "O2[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.25894 0 0 0.25894 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x8" "O2[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x8" "O2[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.25894 0 0 0.25894 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x8" "O2[6]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x8" "O2[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.25894 0 0 0.25894 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x8" "O2[4]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x8" "O2[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.25894 0 0 0.25894 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x8" "O2[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x8" "O2[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.25894 0 0 0.25894 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x8" "O2[5]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x8" "O2[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.25894 0 0 0.25894 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x8" "O1[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x8" "O1[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.25894 0 0 0.25894 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x8" "O1[7]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x8" "O1[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.25894 0 0 0.25894 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x8" "O1[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x8" "O1[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.25894 0 0 0.25894 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x8" "O1[6]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x8" "O1[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.25894 0 0 0.25894 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x8" "O1[4]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x8" "O1[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.25894 0 0 0.25894 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x8" "O1[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x8" "O1[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.25894 0 0 0.25894 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x8" "O1[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x8" "O1[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.25894 0 0 0.25894 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x8" "O1[5]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x8" "O1[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.25894 0 0 0.25894 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x8" "O2[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x8" "O2[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.25894 0 0 0.25894 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x8" "WEB2" '(0 0.1461)
defineDiodeProtection "SRAM2RW16x8" "WEB2" '(0.6)
defineHierAntennaProp "SRAM2RW16x8" "WEB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1461 1.55662 1.03834 0 1.55662 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
)
defineGateSize "SRAM2RW16x8" "WEB1" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineDiodeProtection "SRAM2RW16x8" "WEB1" '(0.6)
defineHierAntennaProp "SRAM2RW16x8" "WEB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1461 1.55812 1.03833 0 1.55812 0 0)
("M3" 0.1461 0.1516 11.7023 0 0.1516 0 0)
("M4" 0.1461 0.1516 12.7391 0 0.1516 0 0)
("M5" 0.1461 0.1516 13.7759 0 0.1516 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x8" "A1[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW16x8" "A1[1]" '(0.6)
defineHierAntennaProp "SRAM2RW16x8" "A1[1]" '(
("M1" 0.0366 0.962918 0 0 0.962918 0 0)
("M2" 0.0366 0.1516 26.3075 0 0.1516 0 0)
("M3" 0.0366 0.1516 30.4476 0 0.1516 0 0)
("M4" 0.0366 0.1516 34.5874 0 0.1516 0 0)
("M5" 0.0366 0.1516 38.7269 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x8" "A1[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW16x8" "A1[2]" '(0.6)
defineHierAntennaProp "SRAM2RW16x8" "A1[2]" '(
("M1" 0.0366 0.962918 0 0 0.962918 0 0)
("M2" 0.0366 0.1516 26.3075 0 0.1516 0 0)
("M3" 0.0366 0.1516 30.4476 0 0.1516 0 0)
("M4" 0.0366 0.1516 34.5874 0 0.1516 0 0)
("M5" 0.0366 0.1516 38.7269 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x8" "A1[3]" '(0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x8" "A1[3]" '(0.6)
defineHierAntennaProp "SRAM2RW16x8" "A1[3]" '(
("M1" 0.021 0.96882 0 0 0.96882 0 0)
("M2" 0.021 0.1516 46.1312 0 0.1516 0 0)
("M3" 0.021 0.1516 53.3468 0 0.1516 0 0)
("M4" 0.021 0.1516 60.5618 0 0.1516 0 0)
("M5" 0.021 0.1516 67.7764 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x8" "I2[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x8" "I2[0]" '(0.6)
defineHierAntennaProp "SRAM2RW16x8" "I2[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28272 1.24827 0 1.28272 0 0)
("M4" 0.021 0.1516 62.3261 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5405 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x8" "I2[7]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x8" "I2[7]" '(0.6)
defineHierAntennaProp "SRAM2RW16x8" "I2[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28272 1.24827 0 1.28272 0 0)
("M4" 0.021 0.1516 62.3261 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5405 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x8" "I2[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x8" "I2[1]" '(0.6)
defineHierAntennaProp "SRAM2RW16x8" "I2[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28272 1.24827 0 1.28272 0 0)
("M4" 0.021 0.1516 62.3261 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5405 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x8" "I2[6]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x8" "I2[6]" '(0.6)
defineHierAntennaProp "SRAM2RW16x8" "I2[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28272 1.24827 0 1.28272 0 0)
("M4" 0.021 0.1516 62.3261 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5405 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x8" "I2[4]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x8" "I2[4]" '(0.6)
defineHierAntennaProp "SRAM2RW16x8" "I2[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28272 1.24827 0 1.28272 0 0)
("M4" 0.021 0.1516 62.3261 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5405 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x8" "I2[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x8" "I2[2]" '(0.6)
defineHierAntennaProp "SRAM2RW16x8" "I2[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28272 1.24827 0 1.28272 0 0)
("M4" 0.021 0.1516 62.3261 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5405 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x8" "I2[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x8" "I2[3]" '(0.6)
defineHierAntennaProp "SRAM2RW16x8" "I2[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28272 1.24827 0 1.28272 0 0)
("M4" 0.021 0.1516 62.3261 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5405 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x8" "I2[5]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x8" "I2[5]" '(0.6)
defineHierAntennaProp "SRAM2RW16x8" "I2[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28272 1.24827 0 1.28272 0 0)
("M4" 0.021 0.1516 62.3261 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5405 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x8" "I1[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x8" "I1[0]" '(0.6)
defineHierAntennaProp "SRAM2RW16x8" "I1[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28272 1.24827 0 1.28272 0 0)
("M4" 0.021 0.1516 62.3261 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5405 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x8" "I1[7]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x8" "I1[7]" '(0.6)
defineHierAntennaProp "SRAM2RW16x8" "I1[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28272 1.24827 0 1.28272 0 0)
("M4" 0.021 0.1516 62.3261 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5405 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x8" "I1[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x8" "I1[1]" '(0.6)
defineHierAntennaProp "SRAM2RW16x8" "I1[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28272 1.24827 0 1.28272 0 0)
("M4" 0.021 0.1516 62.3261 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5405 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x8" "I1[6]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x8" "I1[6]" '(0.6)
defineHierAntennaProp "SRAM2RW16x8" "I1[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28272 1.24827 0 1.28272 0 0)
("M4" 0.021 0.1516 62.3261 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5405 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x8" "I1[4]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x8" "I1[4]" '(0.6)
defineHierAntennaProp "SRAM2RW16x8" "I1[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28272 1.24827 0 1.28272 0 0)
("M4" 0.021 0.1516 62.3261 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5405 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x8" "I1[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x8" "I1[2]" '(0.6)
defineHierAntennaProp "SRAM2RW16x8" "I1[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28272 1.24827 0 1.28272 0 0)
("M4" 0.021 0.1516 62.3261 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5405 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x8" "I1[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x8" "I1[3]" '(0.6)
defineHierAntennaProp "SRAM2RW16x8" "I1[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28272 1.24827 0 1.28272 0 0)
("M4" 0.021 0.1516 62.3261 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5405 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x8" "I1[5]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x8" "I1[5]" '(0.6)
defineHierAntennaProp "SRAM2RW16x8" "I1[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28272 1.24827 0 1.28272 0 0)
("M4" 0.021 0.1516 62.3261 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5405 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x8" "CE2" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineDiodeProtection "SRAM2RW16x8" "CE2" '(0.6)
defineHierAntennaProp "SRAM2RW16x8" "CE2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0342 0.28432 4.84181 0 0.28432 0 0)
("M5" 0.0342 0.1516 13.1544 0 0.1516 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x8" "CSB2" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW16x8" "CSB2" '(0.6)
defineHierAntennaProp "SRAM2RW16x8" "CSB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0366 0.39514 1.96463 0 0.39514 0 0)
("M5" 0.0366 0.1516 12.76 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x8" "CE1" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineDiodeProtection "SRAM2RW16x8" "CE1" '(0.6)
defineHierAntennaProp "SRAM2RW16x8" "CE1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0342 0.2995 4.24673 0 0.2995 0 0)
("M5" 0.0342 0.1516 13.0032 0 0.1516 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x8" "CSB1" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW16x8" "CSB1" '(0.6)
defineHierAntennaProp "SRAM2RW16x8" "CSB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0366 0.39652 1.96517 0 0.39652 0 0)
("M5" 0.0366 0.1516 12.7982 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x8" "A1[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW16x8" "A1[0]" '(0.6)
defineHierAntennaProp "SRAM2RW16x8" "A1[0]" '(
("M1" 0.0366 0.962918 0 0 0.962918 0 0)
("M2" 0.0366 0.1516 26.3075 0 0.1516 0 0)
("M3" 0.0366 0.1516 30.4476 0 0.1516 0 0)
("M4" 0.0366 0.1516 34.5874 0 0.1516 0 0)
("M5" 0.0366 0.1516 38.7269 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x8" "A2[3]" '(0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x8" "A2[3]" '(0.6)
defineHierAntennaProp "SRAM2RW16x8" "A2[3]" '(
("M1" 0.021 0.96757 0 0 0.96757 0 0)
("M2" 0.021 0.1516 46.0717 0 0.1516 0 0)
("M3" 0.021 0.1516 53.2873 0 0.1516 0 0)
("M4" 0.021 0.1516 60.5023 0 0.1516 0 0)
("M5" 0.021 0.1516 67.7169 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x8" "A2[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW16x8" "A2[0]" '(0.6)
defineHierAntennaProp "SRAM2RW16x8" "A2[0]" '(
("M1" 0.0366 0.961668 0 0 0.961668 0 0)
("M2" 0.0366 0.1516 26.2734 0 0.1516 0 0)
("M3" 0.0366 0.1516 30.4134 0 0.1516 0 0)
("M4" 0.0366 0.1516 34.5532 0 0.1516 0 0)
("M5" 0.0366 0.1516 38.6927 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x8" "A2[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW16x8" "A2[1]" '(0.6)
defineHierAntennaProp "SRAM2RW16x8" "A2[1]" '(
("M1" 0.0366 0.961668 0 0 0.961668 0 0)
("M2" 0.0366 0.1516 26.2734 0 0.1516 0 0)
("M3" 0.0366 0.1516 30.4134 0 0.1516 0 0)
("M4" 0.0366 0.1516 34.5532 0 0.1516 0 0)
("M5" 0.0366 0.1516 38.6927 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x8" "A2[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW16x8" "A2[2]" '(0.6)
defineHierAntennaProp "SRAM2RW16x8" "A2[2]" '(
("M1" 0.0366 0.961668 0 0 0.961668 0 0)
("M2" 0.0366 0.1516 26.2734 0 0.1516 0 0)
("M3" 0.0366 0.1516 30.4134 0 0.1516 0 0)
("M4" 0.0366 0.1516 34.5532 0 0.1516 0 0)
("M5" 0.0366 0.1516 38.6927 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x8" "VDD" '(0 0 0 0 3.0816 3.0816 3.0816 3.0816 3.0816 3.0816)
defineDiodeProtection "SRAM2RW16x8" "VDD" '(0 0 0 0 80.28213 80.28213 80.28213 80.28213 80.28213 80.28213)
defineHierAntennaProp "SRAM2RW16x8" "VDD" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 3.0816 938.318 29.0977 0 938.318 0 0)
("M6" 3.0816 0 0 0 0 0 0)
("M7" 3.0816 0 0 0 0 0 0)
("M8" 3.0816 0 0 0 0 0 0)
("M9" 3.0816 0 0 0 0 0 0)
("MRDL" 3.0816 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x8" "VSS" '(0 0 0 0 5.49 5.49 5.49 5.49 5.49 5.49)
defineDiodeProtection "SRAM2RW16x8" "VSS" '(0 0 0 0 62.89692 62.89692 62.89692 62.89692 62.89692 62.89692)
defineHierAntennaProp "SRAM2RW16x8" "VSS" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 5.49 938.336 83.9014 0 938.336 0 0)
("M6" 5.49 0 0 0 0 0 0)
("M7" 5.49 0 0 0 0 0 0)
("M8" 5.49 0 0 0 0 0 0)
("M9" 5.49 0 0 0 0 0 0)
("MRDL" 5.49 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "A1[3]" '(0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW16x16" "A1[3]" '(
("M1" 0.021 0.97687 0 0 0.97687 0 0)
("M2" 0.021 0.1516 46.5146 0 0.1516 0 0)
("M3" 0.021 0.1516 53.7301 0 0.1516 0 0)
("M4" 0.021 0.1516 60.9451 0 0.1516 0 0)
("M5" 0.021 0.1516 68.1596 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "CE1" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineHierAntennaProp "SRAM2RW16x16" "CE1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0342 0.30004 3.80243 0 0.30004 0 0)
("M5" 0.0342 0.1516 12.5747 0 0.1516 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "CSB1" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM2RW16x16" "CSB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0366 0.425149 1.92429 0 0.425149 0 0)
("M5" 0.0366 0.1516 13.5395 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "VDD" '(0 0 0 0 3.0816 3.0816 3.0816 3.0816 3.0816 3.0816)
defineDiodeProtection "SRAM2RW16x16" "VDD" '(0 0 0 0 111.643 111.643 111.643 111.643 111.643 111.643)
defineHierAntennaProp "SRAM2RW16x16" "VDD" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 3.0816 1379.79 29.4592 0 1379.79 0 0)
("M6" 3.0816 0 0 0 0 0 0)
("M7" 3.0816 0 0 0 0 0 0)
("M8" 3.0816 0 0 0 0 0 0)
("M9" 3.0816 0 0 0 0 0 0)
("MRDL" 3.0816 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "I2[15]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW16x16" "I2[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1514 62.3746 0 0.1514 0 0)
("M5" 0.021 0.1514 69.5795 0 0.1514 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "I2[6]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW16x16" "I2[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "CSB2" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM2RW16x16" "CSB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0366 0.40786 1.96052 0 0.40786 0 0)
("M5" 0.0366 0.1516 13.1034 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "CE2" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineHierAntennaProp "SRAM2RW16x16" "CE2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0342 0.31018 3.47688 0 0.31018 0 0)
("M5" 0.0342 0.1516 12.5457 0 0.1516 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "OEB2" '(0 0.2682 0.2682 0.2682 0.2682 0.2682 0.2682 0.2682 0.2682 0.2682)
defineHierAntennaProp "SRAM2RW16x16" "OEB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.2682 1.56088 0.966019 0 1.56088 0 0)
("M3" 0.2682 0.1516 6.78541 0 0.1516 0 0)
("M4" 0.2682 0.1516 7.35017 0 0.1516 0 0)
("M5" 0.2682 0.1516 7.9149 0 0.1516 0 0)
("M6" 0.2682 0 0 0 0 0 0)
("M7" 0.2682 0 0 0 0 0 0)
("M8" 0.2682 0 0 0 0 0 0)
("M9" 0.2682 0 0 0 0 0 0)
("MRDL" 0.2682 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "WEB2" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineHierAntennaProp "SRAM2RW16x16" "WEB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1461 1.57156 1.03834 0 1.57156 0 0)
("M3" 0.1461 0.1516 11.7943 0 0.1516 0 0)
("M4" 0.1461 0.1516 12.8311 0 0.1516 0 0)
("M5" 0.1461 0.1516 13.8678 0 0.1516 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "WEB1" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineHierAntennaProp "SRAM2RW16x16" "WEB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1461 1.5709 1.03834 0 1.5709 0 0)
("M3" 0.1461 0.1516 11.7898 0 0.1516 0 0)
("M4" 0.1461 0.1516 12.8266 0 0.1516 0 0)
("M5" 0.1461 0.1516 13.8633 0 0.1516 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "I1[4]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW16x16" "I1[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "I1[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW16x16" "I1[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "I1[15]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW16x16" "I1[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "I1[6]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x16" "I1[6]" '(0.6)
defineHierAntennaProp "SRAM2RW16x16" "I1[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "I2[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x16" "I2[3]" '(0.6)
defineHierAntennaProp "SRAM2RW16x16" "I2[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "I2[10]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x16" "I2[10]" '(0.6)
defineHierAntennaProp "SRAM2RW16x16" "I2[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "I2[8]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x16" "I2[8]" '(0.6)
defineHierAntennaProp "SRAM2RW16x16" "I2[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "I2[9]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x16" "I2[9]" '(0.6)
defineHierAntennaProp "SRAM2RW16x16" "I2[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "I2[14]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x16" "I2[14]" '(0.6)
defineHierAntennaProp "SRAM2RW16x16" "I2[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "I2[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x16" "I2[0]" '(0.6)
defineHierAntennaProp "SRAM2RW16x16" "I2[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "I2[13]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x16" "I2[13]" '(0.6)
defineHierAntennaProp "SRAM2RW16x16" "I2[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "I2[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x16" "I2[1]" '(0.6)
defineHierAntennaProp "SRAM2RW16x16" "I2[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "I2[5]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x16" "I2[5]" '(0.6)
defineHierAntennaProp "SRAM2RW16x16" "I2[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "I2[7]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x16" "I2[7]" '(0.6)
defineHierAntennaProp "SRAM2RW16x16" "I2[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "I2[12]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x16" "I2[12]" '(0.6)
defineHierAntennaProp "SRAM2RW16x16" "I2[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "I2[11]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x16" "I2[11]" '(0.6)
defineHierAntennaProp "SRAM2RW16x16" "I2[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "I2[4]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x16" "I2[4]" '(0.6)
defineHierAntennaProp "SRAM2RW16x16" "I2[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "I2[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x16" "I2[2]" '(0.6)
defineHierAntennaProp "SRAM2RW16x16" "I2[2]" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x16" "O1[13]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x16" "O1[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x16" "O1[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x16" "O1[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x16" "O1[14]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x16" "O1[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x16" "O1[9]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x16" "O1[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x16" "O1[8]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x16" "O1[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x16" "O1[10]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x16" "O1[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x16" "O1[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x16" "O1[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "I1[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x16" "I1[3]" '(0.6)
defineHierAntennaProp "SRAM2RW16x16" "I1[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "I1[10]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x16" "I1[10]" '(0.6)
defineHierAntennaProp "SRAM2RW16x16" "I1[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "I1[8]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x16" "I1[8]" '(0.6)
defineHierAntennaProp "SRAM2RW16x16" "I1[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "I1[9]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x16" "I1[9]" '(0.6)
defineHierAntennaProp "SRAM2RW16x16" "I1[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "I1[14]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x16" "I1[14]" '(0.6)
defineHierAntennaProp "SRAM2RW16x16" "I1[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "I1[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x16" "I1[0]" '(0.6)
defineHierAntennaProp "SRAM2RW16x16" "I1[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "I1[13]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x16" "I1[13]" '(0.6)
defineHierAntennaProp "SRAM2RW16x16" "I1[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "I1[5]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x16" "I1[5]" '(0.6)
defineHierAntennaProp "SRAM2RW16x16" "I1[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "I1[7]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x16" "I1[7]" '(0.6)
defineHierAntennaProp "SRAM2RW16x16" "I1[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "I1[12]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x16" "I1[12]" '(0.6)
defineHierAntennaProp "SRAM2RW16x16" "I1[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "I1[11]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x16" "I1[11]" '(0.6)
defineHierAntennaProp "SRAM2RW16x16" "I1[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x16" "O2[14]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x16" "O2[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x16" "O2[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x16" "O2[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x16" "O2[13]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x16" "O2[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x16" "O2[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x16" "O2[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x16" "O2[5]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x16" "O2[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x16" "O2[7]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x16" "O2[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x16" "O2[12]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x16" "O2[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x16" "O2[11]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x16" "O2[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x16" "O2[4]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x16" "O2[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x16" "O2[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x16" "O2[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "I1[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x16" "I1[1]" '(0.6)
defineHierAntennaProp "SRAM2RW16x16" "I1[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x16" "O1[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x16" "O1[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x16" "O1[6]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x16" "O1[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x16" "O1[15]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x16" "O1[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x16" "O1[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x16" "O1[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x16" "O1[4]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x16" "O1[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x16" "O1[11]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x16" "O1[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x16" "O1[12]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x16" "O1[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x16" "O1[5]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x16" "O1[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x16" "O1[7]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x16" "O1[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "A1[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW16x16" "A1[0]" '(0.6)
defineHierAntennaProp "SRAM2RW16x16" "A1[0]" '(
("M1" 0.0366 0.970968 0 0 0.970968 0 0)
("M2" 0.0366 0.1516 26.5274 0 0.1516 0 0)
("M3" 0.0366 0.1516 30.6675 0 0.1516 0 0)
("M4" 0.0366 0.1516 34.8073 0 0.1516 0 0)
("M5" 0.0366 0.1516 38.9468 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "A1[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW16x16" "A1[1]" '(0.6)
defineHierAntennaProp "SRAM2RW16x16" "A1[1]" '(
("M1" 0.0366 0.970968 0 0 0.970968 0 0)
("M2" 0.0366 0.1516 26.5274 0 0.1516 0 0)
("M3" 0.0366 0.1516 30.6675 0 0.1516 0 0)
("M4" 0.0366 0.1516 34.8073 0 0.1516 0 0)
("M5" 0.0366 0.1516 38.9468 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "A1[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW16x16" "A1[2]" '(0.6)
defineHierAntennaProp "SRAM2RW16x16" "A1[2]" '(
("M1" 0.0366 0.970968 0 0 0.970968 0 0)
("M2" 0.0366 0.1516 26.5274 0 0.1516 0 0)
("M3" 0.0366 0.1516 30.6675 0 0.1516 0 0)
("M4" 0.0366 0.1516 34.8073 0 0.1516 0 0)
("M5" 0.0366 0.1516 38.9468 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "OEB1" '(0 0.2682 0.2682 0.2682 0.2682 0.2682 0.2682 0.2682 0.2682 0.2682)
defineDiodeProtection "SRAM2RW16x16" "OEB1" '(0.6)
defineHierAntennaProp "SRAM2RW16x16" "OEB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.2682 1.5667 0.96602 0 1.5667 0 0)
("M3" 0.2682 0.1516 6.80711 0 0.1516 0 0)
("M4" 0.2682 0.1516 7.37187 0 0.1516 0 0)
("M5" 0.2682 0.1516 7.9366 0 0.1516 0 0)
("M6" 0.2682 0 0 0 0 0 0)
("M7" 0.2682 0 0 0 0 0 0)
("M8" 0.2682 0 0 0 0 0 0)
("M9" 0.2682 0 0 0 0 0 0)
("MRDL" 0.2682 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x16" "O2[15]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x16" "O2[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x16" "O2[6]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x16" "O2[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "A2[3]" '(0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x16" "A2[3]" '(0.6)
defineHierAntennaProp "SRAM2RW16x16" "A2[3]" '(
("M1" 0.021 0.97742 0 0 0.97742 0 0)
("M2" 0.021 0.1516 46.5407 0 0.1516 0 0)
("M3" 0.021 0.1516 53.7562 0 0.1516 0 0)
("M4" 0.021 0.1516 60.9713 0 0.1516 0 0)
("M5" 0.021 0.1516 68.1858 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "A2[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW16x16" "A2[2]" '(0.6)
defineHierAntennaProp "SRAM2RW16x16" "A2[2]" '(
("M1" 0.0366 0.971518 0 0 0.971518 0 0)
("M2" 0.0366 0.1516 26.5425 0 0.1516 0 0)
("M3" 0.0366 0.1516 30.6825 0 0.1516 0 0)
("M4" 0.0366 0.1516 34.8223 0 0.1516 0 0)
("M5" 0.0366 0.1516 38.9618 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "A2[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW16x16" "A2[1]" '(0.6)
defineHierAntennaProp "SRAM2RW16x16" "A2[1]" '(
("M1" 0.0366 0.971518 0 0 0.971518 0 0)
("M2" 0.0366 0.1516 26.5425 0 0.1516 0 0)
("M3" 0.0366 0.1516 30.6825 0 0.1516 0 0)
("M4" 0.0366 0.1516 34.8223 0 0.1516 0 0)
("M5" 0.0366 0.1516 38.9618 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "A2[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW16x16" "A2[0]" '(0.6)
defineHierAntennaProp "SRAM2RW16x16" "A2[0]" '(
("M1" 0.0366 0.971518 0 0 0.971518 0 0)
("M2" 0.0366 0.1516 26.5425 0 0.1516 0 0)
("M3" 0.0366 0.1516 30.6825 0 0.1516 0 0)
("M4" 0.0366 0.1516 34.8223 0 0.1516 0 0)
("M5" 0.0366 0.1516 38.9618 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x16" "O2[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x16" "O2[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x16" "O2[10]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x16" "O2[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x16" "O2[8]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x16" "O2[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x16" "O2[9]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x16" "O2[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x16" "VSS" '(0 0 0 0 5.49 5.49 5.49 5.49 5.49 5.49)
defineDiodeProtection "SRAM2RW16x16" "VSS" '(0 0 0 0 90.34808 90.34808 90.34808 90.34808 90.34808 90.34808)
defineHierAntennaProp "SRAM2RW16x16" "VSS" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 5.49 1365.44 86.3142 0 1365.44 0 0)
("M6" 5.49 0 0 0 0 0 0)
("M7" 5.49 0 0 0 0 0 0)
("M8" 5.49 0 0 0 0 0 0)
("M9" 5.49 0 0 0 0 0 0)
("MRDL" 5.49 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I1[28]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW16x32" "I1[28]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O1[13]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O1[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O1[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O1[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I1[11]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW16x32" "I1[11]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I1[14]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW16x32" "I1[14]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O1[28]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O1[28]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O1[11]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O1[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I1[23]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW16x32" "I1[23]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O1[25]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O1[25]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I1[25]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW16x32" "I1[25]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O1[4]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O1[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I1[19]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I1[19]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I1[19]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I1[30]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I1[30]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I1[30]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I1[13]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I1[13]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I1[13]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I1[24]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I1[24]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I1[24]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I1[7]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I1[7]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I1[7]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O1[20]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O1[20]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O1[24]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O1[24]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I1[27]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I1[27]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I1[27]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O1[27]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O1[27]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I1[29]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I1[29]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I1[29]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O1[22]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O1[22]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I1[21]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I1[21]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I1[21]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "OEB2" '(0 0.5178 0.5178 0.5178 0.5178 0.5178 0.5178 0.5178 0.5178 0.5178)
defineDiodeProtection "SRAM2RW16x32" "OEB2" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "OEB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.5178 2.88178 0.966022 0 2.88178 0 0)
("M3" 0.5178 0.1516 6.53102 0 0.1516 0 0)
("M4" 0.5178 0.1516 6.82335 0 0.1516 0 0)
("M5" 0.5178 0.1516 7.11566 0 0.1516 0 0)
("M6" 0.5178 0 0 0 0 0 0)
("M7" 0.5178 0 0 0 0 0 0)
("M8" 0.5178 0 0 0 0 0 0)
("M9" 0.5178 0 0 0 0 0 0)
("MRDL" 0.5178 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O1[21]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O1[21]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O1[15]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O1[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O1[29]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O1[29]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O1[23]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O1[23]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I1[26]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I1[26]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I1[26]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.29315 1.24826 0 1.29315 0 0)
("M4" 0.021 0.1512 62.8227 0 0.1512 0 0)
("M5" 0.021 0.1512 70.0181 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O1[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O1[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O1[31]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O1[31]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I1[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I1[0]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I1[0]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I1[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I1[3]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I1[3]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I1[16]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I1[16]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I1[16]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I1[8]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I1[8]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I1[8]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I1[12]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I1[12]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I1[12]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I1[15]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I1[15]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I1[15]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O1[8]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O1[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O1[12]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O1[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O1[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O1[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I1[18]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I1[18]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I1[18]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I1[17]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I1[17]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I1[17]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O1[17]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O1[17]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I2[14]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I2[14]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I2[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O1[9]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O1[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I1[9]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I1[9]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I1[9]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I1[10]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I1[10]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I1[10]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O1[7]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O1[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I1[20]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I1[20]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I1[20]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "A1[3]" '(0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "A1[3]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "A1[3]" '(
("M1" 0.021 1.13705 0 0 1.13705 0 0)
("M2" 0.021 0.1516 54.1417 0 0.1516 0 0)
("M3" 0.021 0.1516 61.3567 0 0.1516 0 0)
("M4" 0.021 0.1516 68.5712 0 0.1516 0 0)
("M5" 0.021 0.1516 75.7852 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "A1[2]" '(0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW16x32" "A1[2]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "A1[2]" '(
("M1" 0 0.9055 0 0 0.9055 0 0)
("M2" 0.0366 0.193696 1.10563 0 0.193696 0 0)
("M3" 0.0366 0.1516 6.39744 0 0.1516 0 0)
("M4" 0.0366 0.1516 10.5388 0 0.1516 0 0)
("M5" 0.0366 0.1516 14.6799 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "A1[1]" '(0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW16x32" "A1[1]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "A1[1]" '(
("M1" 0 0.9055 0 0 0.9055 0 0)
("M2" 0.0366 0.193696 1.10563 0 0.193696 0 0)
("M3" 0.0366 0.1516 6.39744 0 0.1516 0 0)
("M4" 0.0366 0.1516 10.5388 0 0.1516 0 0)
("M5" 0.0366 0.1516 14.6799 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "A1[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW16x32" "A1[0]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "A1[0]" '(
("M1" 0.0366 0.970668 0 0 0.970668 0 0)
("M2" 0.0366 0.1516 26.5192 0 0.1516 0 0)
("M3" 0.0366 0.1516 30.6593 0 0.1516 0 0)
("M4" 0.0366 0.1516 34.7991 0 0.1516 0 0)
("M5" 0.0366 0.1516 38.9386 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "WEB1" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineDiodeProtection "SRAM2RW16x32" "WEB1" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "WEB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1461 1.56742 1.03833 0 1.56742 0 0)
("M3" 0.1461 0.1516 11.766 0 0.1516 0 0)
("M4" 0.1461 0.1516 12.8028 0 0.1516 0 0)
("M5" 0.1461 0.1516 13.8395 0 0.1516 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "CSB2" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW16x32" "CSB2" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "CSB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0366 0.40684 1.96052 0 0.40684 0 0)
("M5" 0.0366 0.1516 13.0755 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "CE2" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineDiodeProtection "SRAM2RW16x32" "CE2" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "CE2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0342 0.30916 3.47688 0 0.30916 0 0)
("M5" 0.0342 0.1516 12.5158 0 0.1516 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "OEB1" '(0 0.5178 0.5178 0.5178 0.5178 0.5178 0.5178 0.5178 0.5178 0.5178)
defineDiodeProtection "SRAM2RW16x32" "OEB1" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "OEB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.5178 2.8876 0.966022 0 2.8876 0 0)
("M3" 0.5178 0.1516 6.54226 0 0.1516 0 0)
("M4" 0.5178 0.1516 6.83459 0 0.1516 0 0)
("M5" 0.5178 0.1516 7.12689 0 0.1516 0 0)
("M6" 0.5178 0 0 0 0 0 0)
("M7" 0.5178 0 0 0 0 0 0)
("M8" 0.5178 0 0 0 0 0 0)
("M9" 0.5178 0 0 0 0 0 0)
("MRDL" 0.5178 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "A2[3]" '(0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "A2[3]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "A2[3]" '(
("M1" 0.021 0.97657 0 0 0.97657 0 0)
("M2" 0.021 0.1516 46.5003 0 0.1516 0 0)
("M3" 0.021 0.1516 53.7158 0 0.1516 0 0)
("M4" 0.021 0.1516 60.9308 0 0.1516 0 0)
("M5" 0.021 0.1516 68.1454 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "A2[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW16x32" "A2[2]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "A2[2]" '(
("M1" 0.0366 0.970668 0 0 0.970668 0 0)
("M2" 0.0366 0.1516 26.5192 0 0.1516 0 0)
("M3" 0.0366 0.1516 30.6593 0 0.1516 0 0)
("M4" 0.0366 0.1516 34.7991 0 0.1516 0 0)
("M5" 0.0366 0.1516 38.9386 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "A2[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW16x32" "A2[0]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "A2[0]" '(
("M1" 0.0366 0.970668 0 0 0.970668 0 0)
("M2" 0.0366 0.1516 26.5192 0 0.1516 0 0)
("M3" 0.0366 0.1516 30.6593 0 0.1516 0 0)
("M4" 0.0366 0.1516 34.7991 0 0.1516 0 0)
("M5" 0.0366 0.1516 38.9386 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "A2[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW16x32" "A2[1]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "A2[1]" '(
("M1" 0.0366 0.970722 0 0 0.970722 0 0)
("M2" 0.0366 0.1516 26.5207 0 0.1516 0 0)
("M3" 0.0366 0.1516 30.6608 0 0.1516 0 0)
("M4" 0.0366 0.1516 34.8005 0 0.1516 0 0)
("M5" 0.0366 0.1516 38.9401 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I2[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I2[3]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I2[3]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O2[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O2[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "VSS" '(0 0 0 0 5.49 5.49 5.49 5.49 5.49 5.49)
defineDiodeProtection "SRAM2RW16x32" "VSS" '(0 0 0 0 145.231 145.231 145.231 145.231 145.231 145.231)
defineHierAntennaProp "SRAM2RW16x32" "VSS" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 5.49 2451.01 82.7751 0 2451.01 0 0)
("M6" 5.49 0 0 0 0 0 0)
("M7" 5.49 0 0 0 0 0 0)
("M8" 5.49 0 0 0 0 0 0)
("M9" 5.49 0 0 0 0 0 0)
("MRDL" 5.49 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "CE1" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineDiodeProtection "SRAM2RW16x32" "CE1" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "CE1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0342 0.29968 3.80244 0 0.29968 0 0)
("M5" 0.0342 0.1516 12.5642 0 0.1516 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I2[13]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I2[13]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I2[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "CSB1" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW16x32" "CSB1" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "CSB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0366 0.424789 1.92429 0 0.424789 0 0)
("M5" 0.0366 0.1516 13.5297 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "VDD" '(0 0 0 0 3.0816 3.0816 3.0816 3.0816 3.0816 3.0816)
defineDiodeProtection "SRAM2RW16x32" "VDD" '(0 0 0 0 174.3454 174.3454 174.3454 174.3454 174.3454 174.3454)
defineHierAntennaProp "SRAM2RW16x32" "VDD" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 3.0816 2451.01 29.5891 0 2451.01 0 0)
("M6" 3.0816 0 0 0 0 0 0)
("M7" 3.0816 0 0 0 0 0 0)
("M8" 3.0816 0 0 0 0 0 0)
("M9" 3.0816 0 0 0 0 0 0)
("MRDL" 3.0816 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I1[4]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I1[4]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I1[4]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O1[16]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O1[16]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O1[10]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O1[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I2[5]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I2[5]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I2[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O2[19]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O2[19]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O2[30]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O2[30]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I2[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I2[1]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I2[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O2[5]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O2[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O2[13]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O2[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O1[18]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O1[18]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I2[31]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I2[31]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I2[31]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I2[19]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I2[19]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I2[19]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O2[6]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O2[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I2[30]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I2[30]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I2[30]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O2[14]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O2[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I2[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I2[2]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I2[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I2[6]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I2[6]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I2[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "WEB2" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineDiodeProtection "SRAM2RW16x32" "WEB2" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "WEB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1461 1.56742 1.03833 0 1.56742 0 0)
("M3" 0.1461 0.1516 11.766 0 0.1516 0 0)
("M4" 0.1461 0.1516 12.8028 0 0.1516 0 0)
("M5" 0.1461 0.1516 13.8395 0 0.1516 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I2[29]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I2[29]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I2[29]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O2[22]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O2[22]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I2[26]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I2[26]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I2[26]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I2[22]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I2[22]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I2[22]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O2[31]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O2[31]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O2[26]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O2[26]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I2[23]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I2[23]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I2[23]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I2[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I2[0]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I2[0]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O2[25]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O2[25]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O2[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O2[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O2[23]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O2[23]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I2[28]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I2[28]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I2[28]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O2[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O2[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O2[4]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O2[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I2[11]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I2[11]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I2[11]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I2[4]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I2[4]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I2[4]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I2[25]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I2[25]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I2[25]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O2[28]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O2[28]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O2[11]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O2[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O2[10]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O2[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O2[9]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O2[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O2[18]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O2[18]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O2[17]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O2[17]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I2[7]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I2[7]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I2[7]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I2[18]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I2[18]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I2[18]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O2[7]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O2[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O2[20]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O2[20]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O2[24]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O2[24]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I2[20]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I2[20]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I2[20]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I2[24]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I2[24]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I2[24]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I2[27]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I2[27]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I2[27]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O2[15]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O2[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O2[27]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O2[27]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I2[21]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I2[21]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I2[21]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I2[15]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I2[15]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I2[15]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O2[29]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O2[29]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O2[21]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O2[21]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O1[5]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O1[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I1[5]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I1[5]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I1[5]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O1[19]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O1[19]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O1[30]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O1[30]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O1[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O1[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O1[6]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O1[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O2[12]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O2[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O1[14]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O1[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I1[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I1[2]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I1[2]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I1[6]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I1[6]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I1[6]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I2[16]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I2[16]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I2[16]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I2[8]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I2[8]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I2[8]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O2[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O2[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O2[16]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O2[16]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O2[8]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O2[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I2[12]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I2[12]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I2[12]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I2[17]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I2[17]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I2[17]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I2[10]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I2[10]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I2[10]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I2[9]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I2[9]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I2[9]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I1[31]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I1[31]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I1[31]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I1[22]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I1[22]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I1[22]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW16x32" "O1[26]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW16x32" "O1[26]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277848 0 0 0.277848 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW16x32" "I1[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW16x32" "I1[1]" '(0.6)
defineHierAntennaProp "SRAM2RW16x32" "I1[1]" '(
("M1" 0 0.1512 0 0 0.1512 0 0)
("M2" 0 0.1512 0 0 0.1512 0 0)
("M3" 0.021 1.28796 1.24826 0 1.28796 0 0)
("M4" 0.021 0.1512 62.5755 0 0.1512 0 0)
("M5" 0.021 0.1512 69.7709 0 0.1512 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x4" "CE2" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineHierAntennaProp "SRAM2RW32x4" "CE2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0342 0.28516 3.92364 0 0.28516 0 0)
("M5" 0.0342 0.1516 12.2608 0 0.1516 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x4" "CSB2" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM2RW32x4" "CSB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0366 0.39598 2.24266 0 0.39598 0 0)
("M5" 0.0366 0.1516 13.0609 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x4" "WEB2" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineHierAntennaProp "SRAM2RW32x4" "WEB2" '(
("M1" 0 0.1514 0 0 0.1514 0 0)
("M2" 0.1461 1.55642 1.03834 0 1.55642 0 0)
("M3" 0.1461 0.1514 11.6907 0 0.1514 0 0)
("M4" 0.1461 0.1514 12.7261 0 0.1514 0 0)
("M5" 0.1461 0.1514 13.7615 0 0.1514 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x4" "I1[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW32x4" "I1[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28362 1.24826 0 1.28362 0 0)
("M4" 0.021 0.1516 62.3689 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5834 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x4" "O1[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x4" "O1[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x4" "CE1" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineHierAntennaProp "SRAM2RW32x4" "CE1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0342 0.29422 3.88652 0 0.29422 0 0)
("M5" 0.0342 0.1516 12.4886 0 0.1516 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x4" "CSB1" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM2RW32x4" "CSB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0366 0.40618 2.49207 0 0.40618 0 0)
("M5" 0.0366 0.1516 13.589 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x4" "A1[3]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM2RW32x4" "A1[3]" '(
("M1" 0.0366 0.895318 0 0 0.895318 0 0)
("M2" 0.0366 0.1516 24.4606 0 0.1516 0 0)
("M3" 0.0366 0.1516 28.6008 0 0.1516 0 0)
("M4" 0.0366 0.1516 32.7407 0 0.1516 0 0)
("M5" 0.0366 0.1516 36.8804 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x4" "A1[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM2RW32x4" "A1[2]" '(
("M1" 0.0366 0.895318 0 0 0.895318 0 0)
("M2" 0.0366 0.1516 24.4606 0 0.1516 0 0)
("M3" 0.0366 0.1516 28.6008 0 0.1516 0 0)
("M4" 0.0366 0.1516 32.7407 0 0.1516 0 0)
("M5" 0.0366 0.1516 36.8804 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x4" "A1[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM2RW32x4" "A1[0]" '(
("M1" 0.0366 0.895318 0 0 0.895318 0 0)
("M2" 0.0366 0.1516 24.4606 0 0.1516 0 0)
("M3" 0.0366 0.1516 28.6008 0 0.1516 0 0)
("M4" 0.0366 0.1516 32.7407 0 0.1516 0 0)
("M5" 0.0366 0.1516 36.8804 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x4" "A1[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM2RW32x4" "A1[1]" '(
("M1" 0.0366 0.895318 0 0 0.895318 0 0)
("M2" 0.0366 0.1516 24.4606 0 0.1516 0 0)
("M3" 0.0366 0.1516 28.6008 0 0.1516 0 0)
("M4" 0.0366 0.1516 32.7407 0 0.1516 0 0)
("M5" 0.0366 0.1516 36.8804 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x4" "A1[4]" '(0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW32x4" "A1[4]" '(
("M1" 0.021 0.97597 0 0 0.97597 0 0)
("M2" 0.021 0.1516 46.4717 0 0.1516 0 0)
("M3" 0.021 0.1516 53.6872 0 0.1516 0 0)
("M4" 0.021 0.1516 60.9022 0 0.1516 0 0)
("M5" 0.021 0.1516 68.1168 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x4" "A2[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x4" "A2[0]" '(0.6)
defineHierAntennaProp "SRAM2RW32x4" "A2[0]" '(
("M1" 0.0366 0.886868 0 0 0.886868 0 0)
("M2" 0.0366 0.1516 24.2298 0 0.1516 0 0)
("M3" 0.0366 0.1516 28.37 0 0.1516 0 0)
("M4" 0.0366 0.1516 32.5099 0 0.1516 0 0)
("M5" 0.0366 0.1516 36.6496 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x4" "A2[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x4" "A2[1]" '(0.6)
defineHierAntennaProp "SRAM2RW32x4" "A2[1]" '(
("M1" 0.0366 0.886868 0 0 0.886868 0 0)
("M2" 0.0366 0.1516 24.2298 0 0.1516 0 0)
("M3" 0.0366 0.1516 28.37 0 0.1516 0 0)
("M4" 0.0366 0.1516 32.5099 0 0.1516 0 0)
("M5" 0.0366 0.1516 36.6496 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x4" "A2[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x4" "A2[2]" '(0.6)
defineHierAntennaProp "SRAM2RW32x4" "A2[2]" '(
("M1" 0.0366 0.886868 0 0 0.886868 0 0)
("M2" 0.0366 0.1516 24.2298 0 0.1516 0 0)
("M3" 0.0366 0.1516 28.37 0 0.1516 0 0)
("M4" 0.0366 0.1516 32.5099 0 0.1516 0 0)
("M5" 0.0366 0.1516 36.6496 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x4" "A2[3]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x4" "A2[3]" '(0.6)
defineHierAntennaProp "SRAM2RW32x4" "A2[3]" '(
("M1" 0.0366 0.886868 0 0 0.886868 0 0)
("M2" 0.0366 0.1516 24.2298 0 0.1516 0 0)
("M3" 0.0366 0.1516 28.37 0 0.1516 0 0)
("M4" 0.0366 0.1516 32.5099 0 0.1516 0 0)
("M5" 0.0366 0.1516 36.6496 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x4" "A2[4]" '(0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x4" "A2[4]" '(0.6)
defineHierAntennaProp "SRAM2RW32x4" "A2[4]" '(
("M1" 0.021 0.96752 0 0 0.96752 0 0)
("M2" 0.021 0.1516 46.0693 0 0.1516 0 0)
("M3" 0.021 0.1516 53.2849 0 0.1516 0 0)
("M4" 0.021 0.1516 60.4999 0 0.1516 0 0)
("M5" 0.021 0.1516 67.7145 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x4" "OEB2" '(0 0.081 0.081 0.081 0.081 0.081 0.081 0.081 0.081 0.081)
defineDiodeProtection "SRAM2RW32x4" "OEB2" '(0.6)
defineHierAntennaProp "SRAM2RW32x4" "OEB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.081 0.57892 0.96601 0 0.57892 0 0)
("M3" 0.081 0.1516 8.11264 0 0.1516 0 0)
("M4" 0.081 0.1516 9.98359 0 0.1516 0 0)
("M5" 0.081 0.1516 11.8544 0 0.1516 0 0)
("M6" 0.081 0 0 0 0 0 0)
("M7" 0.081 0 0 0 0 0 0)
("M8" 0.081 0 0 0 0 0 0)
("M9" 0.081 0 0 0 0 0 0)
("MRDL" 0.081 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x4" "OEB1" '(0 0.081 0.081 0.081 0.081 0.081 0.081 0.081 0.081 0.081)
defineDiodeProtection "SRAM2RW32x4" "OEB1" '(0.6)
defineHierAntennaProp "SRAM2RW32x4" "OEB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.081 0.58474 0.966009 0 0.58474 0 0)
("M3" 0.081 0.1516 8.18449 0 0.1516 0 0)
("M4" 0.081 0.1516 10.0554 0 0.1516 0 0)
("M5" 0.081 0.1516 11.9262 0 0.1516 0 0)
("M6" 0.081 0 0 0 0 0 0)
("M7" 0.081 0 0 0 0 0 0)
("M8" 0.081 0 0 0 0 0 0)
("M9" 0.081 0 0 0 0 0 0)
("MRDL" 0.081 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x4" "WEB1" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineDiodeProtection "SRAM2RW32x4" "WEB1" '(0.6)
defineHierAntennaProp "SRAM2RW32x4" "WEB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1461 1.5667 1.03833 0 1.5667 0 0)
("M3" 0.1461 0.1516 11.761 0 0.1516 0 0)
("M4" 0.1461 0.1516 12.7978 0 0.1516 0 0)
("M5" 0.1461 0.1516 13.8346 0 0.1516 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x4" "O2[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x4" "O2[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277176 0 0 0.277176 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x4" "O2[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x4" "O2[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.275028 0 0 0.275028 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x4" "I2[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x4" "I2[0]" '(0.6)
defineHierAntennaProp "SRAM2RW32x4" "I2[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28362 1.24826 0 1.28362 0 0)
("M4" 0.021 0.1516 62.3689 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5834 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x4" "I2[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x4" "I2[1]" '(0.6)
defineHierAntennaProp "SRAM2RW32x4" "I2[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28362 1.24826 0 1.28362 0 0)
("M4" 0.021 0.1516 62.3689 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5834 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x4" "O2[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x4" "O2[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.27162 0 0 0.27162 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x4" "O1[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x4" "O1[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.276152 0 0 0.276152 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x4" "I1[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x4" "I1[2]" '(0.6)
defineHierAntennaProp "SRAM2RW32x4" "I1[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28362 1.24826 0 1.28362 0 0)
("M4" 0.021 0.1516 62.3689 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5834 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x4" "I1[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x4" "I1[3]" '(0.6)
defineHierAntennaProp "SRAM2RW32x4" "I1[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28362 1.24826 0 1.28362 0 0)
("M4" 0.021 0.1516 62.3689 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5834 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x4" "O1[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x4" "O1[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.273316 0 0 0.273316 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x4" "O1[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x4" "O1[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.270108 0 0 0.270108 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x4" "I1[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x4" "I1[0]" '(0.6)
defineHierAntennaProp "SRAM2RW32x4" "I1[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28362 1.24826 0 1.28362 0 0)
("M4" 0.021 0.1516 62.3689 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5834 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x4" "I2[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x4" "I2[2]" '(0.6)
defineHierAntennaProp "SRAM2RW32x4" "I2[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28362 1.24826 0 1.28362 0 0)
("M4" 0.021 0.1516 62.3689 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5834 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x4" "I2[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x4" "I2[3]" '(0.6)
defineHierAntennaProp "SRAM2RW32x4" "I2[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28362 1.24826 0 1.28362 0 0)
("M4" 0.021 0.1516 62.3689 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5834 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x4" "O2[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x4" "O2[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.275113 0 0 0.275113 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x4" "VDD" '(0 0 0 0 3.0816 3.0816 3.0816 3.0816 3.0816 3.0816)
defineDiodeProtection "SRAM2RW32x4" "VDD" '(0 0 0 0 75.74441 75.74441 75.74441 75.74441 75.74441 75.74441)
defineHierAntennaProp "SRAM2RW32x4" "VDD" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 3.0816 955.566 29.0977 0 955.566 0 0)
("M6" 3.0816 0 0 0 0 0 0)
("M7" 3.0816 0 0 0 0 0 0)
("M8" 3.0816 0 0 0 0 0 0)
("M9" 3.0816 0 0 0 0 0 0)
("MRDL" 3.0816 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x4" "VSS" '(0 0 0 0 5.49 5.49 5.49 5.49 5.49 5.49)
defineDiodeProtection "SRAM2RW32x4" "VSS" '(0 0 0 0 59.91645 59.91645 59.91645 59.91645 59.91645 59.91645)
defineHierAntennaProp "SRAM2RW32x4" "VSS" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 5.49 955.592 86.3142 0 955.592 0 0)
("M6" 5.49 0 0 0 0 0 0)
("M7" 5.49 0 0 0 0 0 0)
("M8" 5.49 0 0 0 0 0 0)
("M9" 5.49 0 0 0 0 0 0)
("MRDL" 5.49 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x8" "O2[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x8" "O2[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.26188 0 0 0.26188 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x8" "OEB2" '(0 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434)
defineHierAntennaProp "SRAM2RW32x8" "OEB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1434 0.90928 0.966015 0 0.90928 0 0)
("M3" 0.1434 0.1516 7.3064 0 0.1516 0 0)
("M4" 0.1434 0.1516 8.36303 0 0.1516 0 0)
("M5" 0.1434 0.1516 9.41959 0 0.1516 0 0)
("M6" 0.1434 0 0 0 0 0 0)
("M7" 0.1434 0 0 0 0 0 0)
("M8" 0.1434 0 0 0 0 0 0)
("M9" 0.1434 0 0 0 0 0 0)
("MRDL" 0.1434 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x8" "WEB2" '(0 0.1461)
defineHierAntennaProp "SRAM2RW32x8" "WEB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1461 1.55662 1.03834 0 1.55662 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
)
defineGateSize "SRAM2RW32x8" "WEB1" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineHierAntennaProp "SRAM2RW32x8" "WEB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1461 1.55818 1.03834 0 1.55818 0 0)
("M3" 0.1461 0.1516 11.7027 0 0.1516 0 0)
("M4" 0.1461 0.1516 12.7395 0 0.1516 0 0)
("M5" 0.1461 0.1516 13.7763 0 0.1516 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x8" "A2[4]" '(0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW32x8" "A2[4]" '(
("M1" 0.021 0.96757 0 0 0.96757 0 0)
("M2" 0.021 0.1516 46.0717 0 0.1516 0 0)
("M3" 0.021 0.1516 53.2873 0 0.1516 0 0)
("M4" 0.021 0.1516 60.5023 0 0.1516 0 0)
("M5" 0.021 0.1516 67.7169 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x8" "I2[5]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW32x8" "I2[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28566 1.24827 0 1.28566 0 0)
("M4" 0.021 0.1516 62.4661 0 0.1516 0 0)
("M5" 0.021 0.1516 69.6805 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x8" "O2[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x8" "O2[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.26188 0 0 0.26188 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x8" "O2[5]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x8" "O2[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.26188 0 0 0.26188 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x8" "I2[6]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW32x8" "I2[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28566 1.24827 0 1.28566 0 0)
("M4" 0.021 0.1516 62.4661 0 0.1516 0 0)
("M5" 0.021 0.1516 69.6805 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x8" "I2[4]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW32x8" "I2[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28566 1.24827 0 1.28566 0 0)
("M4" 0.021 0.1516 62.4661 0 0.1516 0 0)
("M5" 0.021 0.1516 69.6805 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x8" "I2[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW32x8" "I2[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28566 1.24827 0 1.28566 0 0)
("M4" 0.021 0.1516 62.4661 0 0.1516 0 0)
("M5" 0.021 0.1516 69.6805 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x8" "O2[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x8" "O2[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.26188 0 0 0.26188 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x8" "O2[6]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x8" "O2[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.26188 0 0 0.26188 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x8" "O2[4]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x8" "O2[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.26188 0 0 0.26188 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x8" "I2[7]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x8" "I2[7]" '(0.6)
defineHierAntennaProp "SRAM2RW32x8" "I2[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28566 1.24827 0 1.28566 0 0)
("M4" 0.021 0.1516 62.4661 0 0.1516 0 0)
("M5" 0.021 0.1516 69.6805 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x8" "I2[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x8" "I2[0]" '(0.6)
defineHierAntennaProp "SRAM2RW32x8" "I2[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28566 1.24827 0 1.28566 0 0)
("M4" 0.021 0.1516 62.4661 0 0.1516 0 0)
("M5" 0.021 0.1516 69.6805 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x8" "I2[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x8" "I2[1]" '(0.6)
defineHierAntennaProp "SRAM2RW32x8" "I2[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28566 1.24827 0 1.28566 0 0)
("M4" 0.021 0.1516 62.4661 0 0.1516 0 0)
("M5" 0.021 0.1516 69.6805 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x8" "O2[7]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x8" "O2[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.26188 0 0 0.26188 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x8" "CSB2" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x8" "CSB2" '(0.6)
defineHierAntennaProp "SRAM2RW32x8" "CSB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0366 0.39604 1.96052 0 0.39604 0 0)
("M5" 0.0366 0.1516 12.7804 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x8" "CE2" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineDiodeProtection "SRAM2RW32x8" "CE2" '(0.6)
defineHierAntennaProp "SRAM2RW32x8" "CE2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0342 0.29836 3.47688 0 0.29836 0 0)
("M5" 0.0342 0.1516 12.2001 0 0.1516 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x8" "A1[4]" '(0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x8" "A1[4]" '(0.6)
defineHierAntennaProp "SRAM2RW32x8" "A1[4]" '(
("M1" 0.021 0.96887 0 0 0.96887 0 0)
("M2" 0.021 0.1516 46.1336 0 0.1516 0 0)
("M3" 0.021 0.1516 53.3492 0 0.1516 0 0)
("M4" 0.021 0.1516 60.5642 0 0.1516 0 0)
("M5" 0.021 0.1516 67.7788 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x8" "O2[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x8" "O2[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.26188 0 0 0.26188 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x8" "CE1" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineDiodeProtection "SRAM2RW32x8" "CE1" '(0.6)
defineHierAntennaProp "SRAM2RW32x8" "CE1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0342 0.29962 4.24673 0 0.29962 0 0)
("M5" 0.0342 0.1516 13.0067 0 0.1516 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x8" "CSB1" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x8" "CSB1" '(0.6)
defineHierAntennaProp "SRAM2RW32x8" "CSB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0366 0.39658 1.96517 0 0.39658 0 0)
("M5" 0.0366 0.1516 12.7998 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x8" "I1[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x8" "I1[3]" '(0.6)
defineHierAntennaProp "SRAM2RW32x8" "I1[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28566 1.24827 0 1.28566 0 0)
("M4" 0.021 0.1516 62.4661 0 0.1516 0 0)
("M5" 0.021 0.1516 69.6805 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x8" "I1[5]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x8" "I1[5]" '(0.6)
defineHierAntennaProp "SRAM2RW32x8" "I1[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28566 1.24827 0 1.28566 0 0)
("M4" 0.021 0.1516 62.4661 0 0.1516 0 0)
("M5" 0.021 0.1516 69.6805 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x8" "O1[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x8" "O1[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.26188 0 0 0.26188 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x8" "O1[5]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x8" "O1[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.26188 0 0 0.26188 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x8" "O1[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x8" "O1[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.26188 0 0 0.26188 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x8" "I1[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x8" "I1[2]" '(0.6)
defineHierAntennaProp "SRAM2RW32x8" "I1[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28566 1.24827 0 1.28566 0 0)
("M4" 0.021 0.1516 62.4661 0 0.1516 0 0)
("M5" 0.021 0.1516 69.6805 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x8" "I1[4]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x8" "I1[4]" '(0.6)
defineHierAntennaProp "SRAM2RW32x8" "I1[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28566 1.24827 0 1.28566 0 0)
("M4" 0.021 0.1516 62.4661 0 0.1516 0 0)
("M5" 0.021 0.1516 69.6805 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x8" "I1[6]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x8" "I1[6]" '(0.6)
defineHierAntennaProp "SRAM2RW32x8" "I1[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28566 1.24827 0 1.28566 0 0)
("M4" 0.021 0.1516 62.4661 0 0.1516 0 0)
("M5" 0.021 0.1516 69.6805 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x8" "O1[6]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x8" "O1[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.26188 0 0 0.26188 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x8" "O1[4]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x8" "O1[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.26188 0 0 0.26188 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x8" "I1[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x8" "I1[1]" '(0.6)
defineHierAntennaProp "SRAM2RW32x8" "I1[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28566 1.24827 0 1.28566 0 0)
("M4" 0.021 0.1516 62.4661 0 0.1516 0 0)
("M5" 0.021 0.1516 69.6805 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x8" "I1[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x8" "I1[0]" '(0.6)
defineHierAntennaProp "SRAM2RW32x8" "I1[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28566 1.24827 0 1.28566 0 0)
("M4" 0.021 0.1516 62.4661 0 0.1516 0 0)
("M5" 0.021 0.1516 69.6805 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x8" "I1[7]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x8" "I1[7]" '(0.6)
defineHierAntennaProp "SRAM2RW32x8" "I1[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28566 1.24827 0 1.28566 0 0)
("M4" 0.021 0.1516 62.4661 0 0.1516 0 0)
("M5" 0.021 0.1516 69.6805 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x8" "O1[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x8" "O1[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.26188 0 0 0.26188 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x8" "O1[7]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x8" "O1[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.26188 0 0 0.26188 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x8" "O1[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x8" "O1[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.26188 0 0 0.26188 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x8" "I2[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x8" "I2[3]" '(0.6)
defineHierAntennaProp "SRAM2RW32x8" "I2[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28566 1.24827 0 1.28566 0 0)
("M4" 0.021 0.1516 62.4661 0 0.1516 0 0)
("M5" 0.021 0.1516 69.6805 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x8" "OEB1" '(0 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434 0.1434)
defineDiodeProtection "SRAM2RW32x8" "OEB1" '(0.6)
defineHierAntennaProp "SRAM2RW32x8" "OEB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1434 0.9151 0.966016 0 0.9151 0 0)
("M3" 0.1434 0.1516 7.34698 0 0.1516 0 0)
("M4" 0.1434 0.1516 8.40361 0 0.1516 0 0)
("M5" 0.1434 0.1516 9.46017 0 0.1516 0 0)
("M6" 0.1434 0 0 0 0 0 0)
("M7" 0.1434 0 0 0 0 0 0)
("M8" 0.1434 0 0 0 0 0 0)
("M9" 0.1434 0 0 0 0 0 0)
("MRDL" 0.1434 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x8" "A1[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x8" "A1[1]" '(0.6)
defineHierAntennaProp "SRAM2RW32x8" "A1[1]" '(
("M1" 0.0366 0.888218 0 0 0.888218 0 0)
("M2" 0.0366 0.1516 24.2667 0 0.1516 0 0)
("M3" 0.0366 0.1516 28.4069 0 0.1516 0 0)
("M4" 0.0366 0.1516 32.5468 0 0.1516 0 0)
("M5" 0.0366 0.1516 36.6864 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x8" "A1[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x8" "A1[0]" '(0.6)
defineHierAntennaProp "SRAM2RW32x8" "A1[0]" '(
("M1" 0.0366 0.888218 0 0 0.888218 0 0)
("M2" 0.0366 0.1516 24.2667 0 0.1516 0 0)
("M3" 0.0366 0.1516 28.4069 0 0.1516 0 0)
("M4" 0.0366 0.1516 32.5468 0 0.1516 0 0)
("M5" 0.0366 0.1516 36.6864 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x8" "A1[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x8" "A1[2]" '(0.6)
defineHierAntennaProp "SRAM2RW32x8" "A1[2]" '(
("M1" 0.0366 0.888218 0 0 0.888218 0 0)
("M2" 0.0366 0.1516 24.2667 0 0.1516 0 0)
("M3" 0.0366 0.1516 28.4069 0 0.1516 0 0)
("M4" 0.0366 0.1516 32.5468 0 0.1516 0 0)
("M5" 0.0366 0.1516 36.6864 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x8" "A1[3]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x8" "A1[3]" '(0.6)
defineHierAntennaProp "SRAM2RW32x8" "A1[3]" '(
("M1" 0.0366 0.888218 0 0 0.888218 0 0)
("M2" 0.0366 0.1516 24.2667 0 0.1516 0 0)
("M3" 0.0366 0.1516 28.4069 0 0.1516 0 0)
("M4" 0.0366 0.1516 32.5468 0 0.1516 0 0)
("M5" 0.0366 0.1516 36.6864 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x8" "A2[3]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x8" "A2[3]" '(0.6)
defineHierAntennaProp "SRAM2RW32x8" "A2[3]" '(
("M1" 0.0366 0.886918 0 0 0.886918 0 0)
("M2" 0.0366 0.1516 24.2311 0 0.1516 0 0)
("M3" 0.0366 0.1516 28.3713 0 0.1516 0 0)
("M4" 0.0366 0.1516 32.5113 0 0.1516 0 0)
("M5" 0.0366 0.1516 36.6509 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x8" "A2[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x8" "A2[1]" '(0.6)
defineHierAntennaProp "SRAM2RW32x8" "A2[1]" '(
("M1" 0.0366 0.886918 0 0 0.886918 0 0)
("M2" 0.0366 0.1516 24.2311 0 0.1516 0 0)
("M3" 0.0366 0.1516 28.3713 0 0.1516 0 0)
("M4" 0.0366 0.1516 32.5113 0 0.1516 0 0)
("M5" 0.0366 0.1516 36.6509 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x8" "A2[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x8" "A2[2]" '(0.6)
defineHierAntennaProp "SRAM2RW32x8" "A2[2]" '(
("M1" 0.0366 0.886918 0 0 0.886918 0 0)
("M2" 0.0366 0.1516 24.2311 0 0.1516 0 0)
("M3" 0.0366 0.1516 28.3713 0 0.1516 0 0)
("M4" 0.0366 0.1516 32.5113 0 0.1516 0 0)
("M5" 0.0366 0.1516 36.6509 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x8" "A2[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x8" "A2[0]" '(0.6)
defineHierAntennaProp "SRAM2RW32x8" "A2[0]" '(
("M1" 0.0366 0.886918 0 0 0.886918 0 0)
("M2" 0.0366 0.1516 24.2311 0 0.1516 0 0)
("M3" 0.0366 0.1516 28.3713 0 0.1516 0 0)
("M4" 0.0366 0.1516 32.5113 0 0.1516 0 0)
("M5" 0.0366 0.1516 36.6509 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x8" "VDD" '(0 0 0 0 3.0816 3.0816 3.0816 3.0816 3.0816 3.0816)
defineDiodeProtection "SRAM2RW32x8" "VDD" '(0 0 0 0 95.57189 95.57189 95.57189 95.57189 95.57189 95.57189)
defineHierAntennaProp "SRAM2RW32x8" "VDD" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 3.0816 1192.32 29.2071 0 1192.32 0 0)
("M6" 3.0816 0 0 0 0 0 0)
("M7" 3.0816 0 0 0 0 0 0)
("M8" 3.0816 0 0 0 0 0 0)
("M9" 3.0816 0 0 0 0 0 0)
("MRDL" 3.0816 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x8" "VSS" '(0 0 0 0 5.49 5.49 5.49 5.49 5.49 5.49)
defineDiodeProtection "SRAM2RW32x8" "VSS" '(0 0 0 0 79.61691 79.61691 79.61691 79.61691 79.61691 79.61691)
defineHierAntennaProp "SRAM2RW32x8" "VSS" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 5.49 1192.31 84.027 0 1192.31 0 0)
("M6" 5.49 0 0 0 0 0 0)
("M7" 5.49 0 0 0 0 0 0)
("M8" 5.49 0 0 0 0 0 0)
("M9" 5.49 0 0 0 0 0 0)
("MRDL" 5.49 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x16" "O1[8]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x16" "O1[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "VSS" '(0 0 0 0 5.1498 5.1498 5.1498 5.1498 5.1498 5.1498)
defineDiodeProtection "SRAM2RW32x16" "VSS" '(0 0 0 0 116.9174 116.9174 116.9174 116.9174 116.9174 116.9174)
defineHierAntennaProp "SRAM2RW32x16" "VSS" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 5.1498 1719.25 86.3143 0 1719.25 0 0)
("M6" 5.1498 0 0 0 0 0 0)
("M7" 5.1498 0 0 0 0 0 0)
("M8" 5.1498 0 0 0 0 0 0)
("M9" 5.1498 0 0 0 0 0 0)
("MRDL" 5.1498 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "A2[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM2RW32x16" "A2[2]" '(
("M1" 0.0366 0.900468 0 0 0.900468 0 0)
("M2" 0.0366 0.1516 24.6013 0 0.1516 0 0)
("M3" 0.0366 0.1516 28.7415 0 0.1516 0 0)
("M4" 0.0366 0.1516 32.8814 0 0.1516 0 0)
("M5" 0.0366 0.1516 37.021 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "A2[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM2RW32x16" "A2[1]" '(
("M1" 0.0366 0.900468 0 0 0.900468 0 0)
("M2" 0.0366 0.1516 24.6013 0 0.1516 0 0)
("M3" 0.0366 0.1516 28.7415 0 0.1516 0 0)
("M4" 0.0366 0.1516 32.8814 0 0.1516 0 0)
("M5" 0.0366 0.1516 37.021 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "A2[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM2RW32x16" "A2[0]" '(
("M1" 0.0366 0.900468 0 0 0.900468 0 0)
("M2" 0.0366 0.1516 24.6013 0 0.1516 0 0)
("M3" 0.0366 0.1516 28.7415 0 0.1516 0 0)
("M4" 0.0366 0.1516 32.8814 0 0.1516 0 0)
("M5" 0.0366 0.1516 37.021 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "VDD" '(0 0 0 0 3.0816 3.0816 3.0816 3.0816 3.0816 3.0816)
defineDiodeProtection "SRAM2RW32x16" "VDD" '(0 0 0 0 135.2333 135.2333 135.2333 135.2333 135.2333 135.2333)
defineHierAntennaProp "SRAM2RW32x16" "VDD" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 3.0816 1737.38 29.4593 0 1737.38 0 0)
("M6" 3.0816 0 0 0 0 0 0)
("M7" 3.0816 0 0 0 0 0 0)
("M8" 3.0816 0 0 0 0 0 0)
("M9" 3.0816 0 0 0 0 0 0)
("MRDL" 3.0816 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x16" "O2[15]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x16" "O2[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "I2[6]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW32x16" "I2[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x16" "O2[6]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x16" "O2[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "I2[15]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW32x16" "I2[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1514 62.3746 0 0.1514 0 0)
("M5" 0.021 0.1514 69.5795 0 0.1514 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "I2[4]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW32x16" "I2[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "OEB2" '(0 0.2682 0.2682 0.2682 0.2682 0.2682 0.2682 0.2682 0.2682 0.2682)
defineHierAntennaProp "SRAM2RW32x16" "OEB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.2682 1.56088 0.966019 0 1.56088 0 0)
("M3" 0.2682 0.1516 6.78541 0 0.1516 0 0)
("M4" 0.2682 0.1516 7.35017 0 0.1516 0 0)
("M5" 0.2682 0.1516 7.9149 0 0.1516 0 0)
("M6" 0.2682 0 0 0 0 0 0)
("M7" 0.2682 0 0 0 0 0 0)
("M8" 0.2682 0 0 0 0 0 0)
("M9" 0.2682 0 0 0 0 0 0)
("MRDL" 0.2682 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "OEB1" '(0 0.2682 0.2682 0.2682 0.2682 0.2682 0.2682 0.2682 0.2682 0.2682)
defineHierAntennaProp "SRAM2RW32x16" "OEB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.2682 1.5667 0.96602 0 1.5667 0 0)
("M3" 0.2682 0.1516 6.80711 0 0.1516 0 0)
("M4" 0.2682 0.1516 7.37187 0 0.1516 0 0)
("M5" 0.2682 0.1516 7.9366 0 0.1516 0 0)
("M6" 0.2682 0 0 0 0 0 0)
("M7" 0.2682 0 0 0 0 0 0)
("M8" 0.2682 0 0 0 0 0 0)
("M9" 0.2682 0 0 0 0 0 0)
("MRDL" 0.2682 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "WEB1" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineDiodeProtection "SRAM2RW32x16" "WEB1" '(0.6)
defineHierAntennaProp "SRAM2RW32x16" "WEB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1461 1.5709 1.03834 0 1.5709 0 0)
("M3" 0.1461 0.1516 11.7898 0 0.1516 0 0)
("M4" 0.1461 0.1516 12.8266 0 0.1516 0 0)
("M5" 0.1461 0.1516 13.8633 0 0.1516 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "WEB2" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineDiodeProtection "SRAM2RW32x16" "WEB2" '(0.6)
defineHierAntennaProp "SRAM2RW32x16" "WEB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1461 1.576 1.03834 0 1.576 0 0)
("M3" 0.1461 0.1516 11.8247 0 0.1516 0 0)
("M4" 0.1461 0.1516 12.8615 0 0.1516 0 0)
("M5" 0.1461 0.1516 13.8982 0 0.1516 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x16" "O2[8]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x16" "O2[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x16" "O2[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x16" "O2[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "I2[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x16" "I2[1]" '(0.6)
defineHierAntennaProp "SRAM2RW32x16" "I2[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "I2[13]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x16" "I2[13]" '(0.6)
defineHierAntennaProp "SRAM2RW32x16" "I2[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x16" "O2[5]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x16" "O2[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "I2[14]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x16" "I2[14]" '(0.6)
defineHierAntennaProp "SRAM2RW32x16" "I2[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x16" "O2[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x16" "O2[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "I2[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x16" "I2[0]" '(0.6)
defineHierAntennaProp "SRAM2RW32x16" "I2[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x16" "O2[13]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x16" "O2[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x16" "O2[11]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x16" "O2[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "I2[11]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x16" "I2[11]" '(0.6)
defineHierAntennaProp "SRAM2RW32x16" "I2[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "I2[12]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x16" "I2[12]" '(0.6)
defineHierAntennaProp "SRAM2RW32x16" "I2[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x16" "O2[12]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x16" "O2[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x16" "O2[4]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x16" "O2[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "I2[7]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x16" "I2[7]" '(0.6)
defineHierAntennaProp "SRAM2RW32x16" "I2[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "I2[5]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x16" "I2[5]" '(0.6)
defineHierAntennaProp "SRAM2RW32x16" "I2[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x16" "O2[7]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x16" "O2[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x16" "O2[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x16" "O2[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "I1[7]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x16" "I1[7]" '(0.6)
defineHierAntennaProp "SRAM2RW32x16" "I1[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x16" "O1[11]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x16" "O1[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "I1[11]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x16" "I1[11]" '(0.6)
defineHierAntennaProp "SRAM2RW32x16" "I1[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x16" "O1[4]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x16" "O1[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "I1[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x16" "I1[2]" '(0.6)
defineHierAntennaProp "SRAM2RW32x16" "I1[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x16" "O1[15]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x16" "O1[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "I1[15]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x16" "I1[15]" '(0.6)
defineHierAntennaProp "SRAM2RW32x16" "I1[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x16" "O1[6]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x16" "O1[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "I1[6]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x16" "I1[6]" '(0.6)
defineHierAntennaProp "SRAM2RW32x16" "I1[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x16" "O2[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x16" "O2[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "I1[4]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x16" "I1[4]" '(0.6)
defineHierAntennaProp "SRAM2RW32x16" "I1[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x16" "O1[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x16" "O1[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "I2[9]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x16" "I2[9]" '(0.6)
defineHierAntennaProp "SRAM2RW32x16" "I2[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x16" "O2[14]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x16" "O2[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "I2[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x16" "I2[3]" '(0.6)
defineHierAntennaProp "SRAM2RW32x16" "I2[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x16" "O2[10]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x16" "O2[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "I2[10]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x16" "I2[10]" '(0.6)
defineHierAntennaProp "SRAM2RW32x16" "I2[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x16" "O2[9]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x16" "O2[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "I2[8]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x16" "I2[8]" '(0.6)
defineHierAntennaProp "SRAM2RW32x16" "I2[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "I1[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x16" "I1[3]" '(0.6)
defineHierAntennaProp "SRAM2RW32x16" "I1[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x16" "O1[14]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x16" "O1[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x16" "O1[10]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x16" "O1[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "I1[8]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x16" "I1[8]" '(0.6)
defineHierAntennaProp "SRAM2RW32x16" "I1[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x16" "O1[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x16" "O1[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x16" "O1[9]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x16" "O1[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "I1[9]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x16" "I1[9]" '(0.6)
defineHierAntennaProp "SRAM2RW32x16" "I1[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "I1[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x16" "I1[1]" '(0.6)
defineHierAntennaProp "SRAM2RW32x16" "I1[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x16" "O1[13]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x16" "O1[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "I1[13]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x16" "I1[13]" '(0.6)
defineHierAntennaProp "SRAM2RW32x16" "I1[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x16" "O1[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x16" "O1[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "I1[14]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x16" "I1[14]" '(0.6)
defineHierAntennaProp "SRAM2RW32x16" "I1[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x16" "O1[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x16" "O1[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x16" "O1[5]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x16" "O1[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "I1[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x16" "I1[0]" '(0.6)
defineHierAntennaProp "SRAM2RW32x16" "I1[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x16" "O1[12]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x16" "O1[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "I1[12]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x16" "I1[12]" '(0.6)
defineHierAntennaProp "SRAM2RW32x16" "I1[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "I1[5]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x16" "I1[5]" '(0.6)
defineHierAntennaProp "SRAM2RW32x16" "I1[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x16" "O1[7]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x16" "O1[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.274264 0 0 0.274264 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "A2[3]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x16" "A2[3]" '(0.6)
defineHierAntennaProp "SRAM2RW32x16" "A2[3]" '(
("M1" 0.0366 0.900468 0 0 0.900468 0 0)
("M2" 0.0366 0.1516 24.6013 0 0.1516 0 0)
("M3" 0.0366 0.1516 28.7415 0 0.1516 0 0)
("M4" 0.0366 0.1516 32.8814 0 0.1516 0 0)
("M5" 0.0366 0.1516 37.021 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "A2[4]" '(0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x16" "A2[4]" '(0.6)
defineHierAntennaProp "SRAM2RW32x16" "A2[4]" '(
("M1" 0.021 0.98112 0 0 0.98112 0 0)
("M2" 0.021 0.1516 46.7169 0 0.1516 0 0)
("M3" 0.021 0.1516 53.9324 0 0.1516 0 0)
("M4" 0.021 0.1516 61.1474 0 0.1516 0 0)
("M5" 0.021 0.1516 68.362 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "CE2" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineDiodeProtection "SRAM2RW32x16" "CE2" '(0.6)
defineHierAntennaProp "SRAM2RW32x16" "CE2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0342 0.31462 3.47688 0 0.31462 0 0)
("M5" 0.0342 0.1516 12.6755 0 0.1516 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "CSB2" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x16" "CSB2" '(0.6)
defineHierAntennaProp "SRAM2RW32x16" "CSB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0366 0.4123 1.96053 0 0.4123 0 0)
("M5" 0.0366 0.1516 13.2247 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "A1[3]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x16" "A1[3]" '(0.6)
defineHierAntennaProp "SRAM2RW32x16" "A1[3]" '(
("M1" 0.0366 0.896218 0 0 0.896218 0 0)
("M2" 0.0366 0.1516 24.4852 0 0.1516 0 0)
("M3" 0.0366 0.1516 28.6254 0 0.1516 0 0)
("M4" 0.0366 0.1516 32.7653 0 0.1516 0 0)
("M5" 0.0366 0.1516 36.905 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "A1[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x16" "A1[0]" '(0.6)
defineHierAntennaProp "SRAM2RW32x16" "A1[0]" '(
("M1" 0.0366 0.896218 0 0 0.896218 0 0)
("M2" 0.0366 0.1516 24.4852 0 0.1516 0 0)
("M3" 0.0366 0.1516 28.6254 0 0.1516 0 0)
("M4" 0.0366 0.1516 32.7653 0 0.1516 0 0)
("M5" 0.0366 0.1516 36.905 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "A1[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x16" "A1[2]" '(0.6)
defineHierAntennaProp "SRAM2RW32x16" "A1[2]" '(
("M1" 0.0366 0.896218 0 0 0.896218 0 0)
("M2" 0.0366 0.1516 24.4852 0 0.1516 0 0)
("M3" 0.0366 0.1516 28.6254 0 0.1516 0 0)
("M4" 0.0366 0.1516 32.7653 0 0.1516 0 0)
("M5" 0.0366 0.1516 36.905 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "A1[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x16" "A1[1]" '(0.6)
defineHierAntennaProp "SRAM2RW32x16" "A1[1]" '(
("M1" 0.0366 0.896218 0 0 0.896218 0 0)
("M2" 0.0366 0.1516 24.4852 0 0.1516 0 0)
("M3" 0.0366 0.1516 28.6254 0 0.1516 0 0)
("M4" 0.0366 0.1516 32.7653 0 0.1516 0 0)
("M5" 0.0366 0.1516 36.905 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "A1[4]" '(0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x16" "A1[4]" '(0.6)
defineHierAntennaProp "SRAM2RW32x16" "A1[4]" '(
("M1" 0.021 0.97687 0 0 0.97687 0 0)
("M2" 0.021 0.1516 46.5146 0 0.1516 0 0)
("M3" 0.021 0.1516 53.7301 0 0.1516 0 0)
("M4" 0.021 0.1516 60.9451 0 0.1516 0 0)
("M5" 0.021 0.1516 68.1596 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "CE1" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineDiodeProtection "SRAM2RW32x16" "CE1" '(0.6)
defineHierAntennaProp "SRAM2RW32x16" "CE1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0342 0.30004 3.80243 0 0.30004 0 0)
("M5" 0.0342 0.1516 12.5747 0 0.1516 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "CSB1" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x16" "CSB1" '(0.6)
defineHierAntennaProp "SRAM2RW32x16" "CSB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0366 0.425149 1.92429 0 0.425149 0 0)
("M5" 0.0366 0.1516 13.5395 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "I2[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x16" "I2[2]" '(0.6)
defineHierAntennaProp "SRAM2RW32x16" "I2[2]" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x16" "I1[10]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x16" "I1[10]" '(0.6)
defineHierAntennaProp "SRAM2RW32x16" "I1[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28374 1.24826 0 1.28374 0 0)
("M4" 0.021 0.1516 62.3746 0 0.1516 0 0)
("M5" 0.021 0.1516 69.5891 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I2[17]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW32x32" "I2[17]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O2[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O2[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O2[9]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O2[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O2[10]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O2[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I2[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW32x32" "I2[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I2[9]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW32x32" "I2[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I2[10]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW32x32" "I2[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O2[17]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O2[17]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O2[16]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O2[16]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I2[16]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW32x32" "I2[16]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O2[12]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O2[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O2[8]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O2[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I2[12]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I2[12]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I2[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I2[8]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I2[8]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I2[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O1[6]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O1[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I2[31]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I2[31]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I2[31]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I2[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I2[0]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I2[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I2[23]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I2[23]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I2[23]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O2[26]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O2[26]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I2[21]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I2[21]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I2[21]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I2[22]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I2[22]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I2[22]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I2[29]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I2[29]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I2[29]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O2[21]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O2[21]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O2[29]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O2[29]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O2[22]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O2[22]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O2[15]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O2[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I2[27]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I2[27]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I2[27]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I2[15]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I2[15]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I2[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O2[20]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O2[20]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O2[27]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O2[27]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I2[24]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I2[24]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I2[24]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I2[20]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I2[20]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I2[20]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I2[18]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I2[18]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I2[18]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O2[5]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O2[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O2[30]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O2[30]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I2[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I2[1]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I2[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "A1[4]" '(0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "A1[4]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "A1[4]" '(
("M1" 0.021 0.97657 0 0 0.97657 0 0)
("M2" 0.021 0.1516 46.5003 0 0.1516 0 0)
("M3" 0.021 0.1516 53.7158 0 0.1516 0 0)
("M4" 0.021 0.1516 60.9308 0 0.1516 0 0)
("M5" 0.021 0.1516 68.1454 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I2[5]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I2[5]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I2[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I2[30]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I2[30]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I2[30]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O2[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O2[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O2[4]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O2[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O2[11]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O2[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O2[28]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O2[28]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I2[25]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I2[25]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I2[25]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I2[4]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I2[4]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I2[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I2[11]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I2[11]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I2[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I2[28]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I2[28]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I2[28]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O2[31]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O2[31]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O2[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O2[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O2[23]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O2[23]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O2[25]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O2[25]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I2[26]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I2[26]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I2[26]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O1[10]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O1[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O2[6]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O2[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I2[6]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I2[6]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I2[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I1[4]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I1[4]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I1[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "CSB2" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x32" "CSB2" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "CSB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0366 0.40684 1.96052 0 0.40684 0 0)
("M5" 0.0366 0.1516 13.0755 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I2[13]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I2[13]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I2[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I2[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I2[2]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I2[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O2[19]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O2[19]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O2[14]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O2[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I2[19]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I2[19]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I2[19]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I2[14]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I2[14]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I2[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28812 1.24826 0 1.28812 0 0)
("M4" 0.021 0.1516 62.5832 0 0.1516 0 0)
("M5" 0.021 0.1516 69.7976 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O2[13]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O2[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "VSS" '(0 0 0 0 5.49 5.49 5.49 5.49 5.49 5.49)
defineDiodeProtection "SRAM2RW32x32" "VSS" '(0 0 0 0 197.8197 197.8197 197.8197 197.8197 197.8197 197.8197)
defineHierAntennaProp "SRAM2RW32x32" "VSS" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 5.49 3010.76 82.7751 0 3010.76 0 0)
("M6" 5.49 0 0 0 0 0 0)
("M7" 5.49 0 0 0 0 0 0)
("M8" 5.49 0 0 0 0 0 0)
("M9" 5.49 0 0 0 0 0 0)
("MRDL" 5.49 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "CE1" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineDiodeProtection "SRAM2RW32x32" "CE1" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "CE1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0342 0.29968 3.80244 0 0.29968 0 0)
("M5" 0.0342 0.1516 12.5642 0 0.1516 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "WEB2" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineDiodeProtection "SRAM2RW32x32" "WEB2" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "WEB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1461 1.56742 1.03833 0 1.56742 0 0)
("M3" 0.1461 0.1516 11.766 0 0.1516 0 0)
("M4" 0.1461 0.1516 12.8028 0 0.1516 0 0)
("M5" 0.1461 0.1516 13.8395 0 0.1516 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O1[16]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O1[16]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "CSB1" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x32" "CSB1" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "CSB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0366 0.424789 1.92429 0 0.424789 0 0)
("M5" 0.0366 0.1516 13.5297 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "VDD" '(0 0 0 0 3.0816 3.0816 3.0816 3.0816 3.0816 3.0816)
defineDiodeProtection "SRAM2RW32x32" "VDD" '(0 0 0 0 214.5368 214.5368 214.5368 214.5368 214.5368 214.5368)
defineHierAntennaProp "SRAM2RW32x32" "VDD" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 3.0816 3010.26 29.589 0 3010.26 0 0)
("M6" 3.0816 0 0 0 0 0 0)
("M7" 3.0816 0 0 0 0 0 0)
("M8" 3.0816 0 0 0 0 0 0)
("M9" 3.0816 0 0 0 0 0 0)
("MRDL" 3.0816 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O1[12]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O1[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O2[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O2[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I1[8]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I1[8]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I1[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I1[16]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I1[16]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I1[16]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I1[12]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I1[12]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I1[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "WEB1" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineDiodeProtection "SRAM2RW32x32" "WEB1" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "WEB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1461 1.56742 1.03833 0 1.56742 0 0)
("M3" 0.1461 0.1516 11.766 0 0.1516 0 0)
("M4" 0.1461 0.1516 12.8028 0 0.1516 0 0)
("M5" 0.1461 0.1516 13.8395 0 0.1516 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "A1[3]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x32" "A1[3]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "A1[3]" '(
("M1" 0.0366 0.895918 0 0 0.895918 0 0)
("M2" 0.0366 0.1516 24.477 0 0.1516 0 0)
("M3" 0.0366 0.1516 28.6172 0 0.1516 0 0)
("M4" 0.0366 0.1516 32.7571 0 0.1516 0 0)
("M5" 0.0366 0.1516 36.8968 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "A1[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x32" "A1[2]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "A1[2]" '(
("M1" 0.0366 0.895918 0 0 0.895918 0 0)
("M2" 0.0366 0.1516 24.477 0 0.1516 0 0)
("M3" 0.0366 0.1516 28.6172 0 0.1516 0 0)
("M4" 0.0366 0.1516 32.7571 0 0.1516 0 0)
("M5" 0.0366 0.1516 36.8968 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "OEB2" '(0 0.5178 0.5178 0.5178 0.5178 0.5178 0.5178 0.5178 0.5178 0.5178)
defineDiodeProtection "SRAM2RW32x32" "OEB2" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "OEB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.5178 2.88178 0.966022 0 2.88178 0 0)
("M3" 0.5178 0.1516 6.53102 0 0.1516 0 0)
("M4" 0.5178 0.1516 6.82335 0 0.1516 0 0)
("M5" 0.5178 0.1516 7.11566 0 0.1516 0 0)
("M6" 0.5178 0 0 0 0 0 0)
("M7" 0.5178 0 0 0 0 0 0)
("M8" 0.5178 0 0 0 0 0 0)
("M9" 0.5178 0 0 0 0 0 0)
("MRDL" 0.5178 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I1[15]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I1[15]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I1[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "A1[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x32" "A1[0]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "A1[0]" '(
("M1" 0.0366 0.895918 0 0 0.895918 0 0)
("M2" 0.0366 0.1516 24.477 0 0.1516 0 0)
("M3" 0.0366 0.1516 28.6172 0 0.1516 0 0)
("M4" 0.0366 0.1516 32.7571 0 0.1516 0 0)
("M5" 0.0366 0.1516 36.8968 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "A2[3]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x32" "A2[3]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "A2[3]" '(
("M1" 0.0366 0.895918 0 0 0.895918 0 0)
("M2" 0.0366 0.1516 24.477 0 0.1516 0 0)
("M3" 0.0366 0.1516 28.6172 0 0.1516 0 0)
("M4" 0.0366 0.1516 32.7571 0 0.1516 0 0)
("M5" 0.0366 0.1516 36.8968 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "A2[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x32" "A2[2]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "A2[2]" '(
("M1" 0.0366 0.895918 0 0 0.895918 0 0)
("M2" 0.0366 0.1516 24.477 0 0.1516 0 0)
("M3" 0.0366 0.1516 28.6172 0 0.1516 0 0)
("M4" 0.0366 0.1516 32.7571 0 0.1516 0 0)
("M5" 0.0366 0.1516 36.8968 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "A2[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x32" "A2[1]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "A2[1]" '(
("M1" 0.0366 0.895918 0 0 0.895918 0 0)
("M2" 0.0366 0.1516 24.477 0 0.1516 0 0)
("M3" 0.0366 0.1516 28.6172 0 0.1516 0 0)
("M4" 0.0366 0.1516 32.7571 0 0.1516 0 0)
("M5" 0.0366 0.1516 36.8968 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "A2[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x32" "A2[0]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "A2[0]" '(
("M1" 0.0366 0.895918 0 0 0.895918 0 0)
("M2" 0.0366 0.1516 24.477 0 0.1516 0 0)
("M3" 0.0366 0.1516 28.6172 0 0.1516 0 0)
("M4" 0.0366 0.1516 32.7571 0 0.1516 0 0)
("M5" 0.0366 0.1516 36.8968 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "A1[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x32" "A1[1]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "A1[1]" '(
("M1" 0.0366 0.895918 0 0 0.895918 0 0)
("M2" 0.0366 0.1516 24.477 0 0.1516 0 0)
("M3" 0.0366 0.1516 28.6172 0 0.1516 0 0)
("M4" 0.0366 0.1516 32.7571 0 0.1516 0 0)
("M5" 0.0366 0.1516 36.8968 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "CE2" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineDiodeProtection "SRAM2RW32x32" "CE2" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "CE2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0342 0.30916 3.47688 0 0.30916 0 0)
("M5" 0.0342 0.1516 12.5158 0 0.1516 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "A2[4]" '(0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "A2[4]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "A2[4]" '(
("M1" 0.021 0.97657 0 0 0.97657 0 0)
("M2" 0.021 0.1516 46.5003 0 0.1516 0 0)
("M3" 0.021 0.1516 53.7158 0 0.1516 0 0)
("M4" 0.021 0.1516 60.9308 0 0.1516 0 0)
("M5" 0.021 0.1516 68.1454 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "OEB1" '(0 0.5178 0.5178 0.5178 0.5178 0.5178 0.5178 0.5178 0.5178 0.5178)
defineDiodeProtection "SRAM2RW32x32" "OEB1" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "OEB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.5178 2.8876 0.966022 0 2.8876 0 0)
("M3" 0.5178 0.1516 6.54226 0 0.1516 0 0)
("M4" 0.5178 0.1516 6.83459 0 0.1516 0 0)
("M5" 0.5178 0.1516 7.12689 0 0.1516 0 0)
("M6" 0.5178 0 0 0 0 0 0)
("M7" 0.5178 0 0 0 0 0 0)
("M8" 0.5178 0 0 0 0 0 0)
("M9" 0.5178 0 0 0 0 0 0)
("MRDL" 0.5178 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I1[21]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I1[21]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I1[21]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O1[27]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O1[27]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O1[20]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O1[20]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I1[20]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I1[20]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I1[20]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O1[24]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O1[24]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I1[24]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I1[24]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I1[24]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O1[18]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O1[18]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O1[7]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O1[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I1[17]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I1[17]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I1[17]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I1[18]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I1[18]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I1[18]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I1[7]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I1[7]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I1[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I1[10]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I1[10]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I1[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I1[9]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I1[9]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I1[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O1[17]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O1[17]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O1[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O1[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O1[9]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O1[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I1[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I1[3]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I1[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O1[8]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O1[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I1[11]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I1[11]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I1[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I1[28]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I1[28]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I1[28]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I1[25]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I1[25]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I1[25]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I1[31]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I1[31]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I1[31]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I1[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I1[0]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I1[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I1[23]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I1[23]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I1[23]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O1[31]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O1[31]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O1[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O1[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O1[23]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O1[23]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I1[26]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I1[26]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I1[26]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.29343 1.24826 0 1.29343 0 0)
("M4" 0.021 0.1516 62.836 0 0.1516 0 0)
("M5" 0.021 0.1516 70.0504 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O1[25]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O1[25]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O1[29]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O1[29]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O1[22]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O1[22]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O1[26]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O1[26]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I1[29]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I1[29]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I1[29]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I1[22]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I1[22]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I1[22]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O1[15]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O1[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O1[21]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O1[21]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I1[27]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I1[27]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I1[27]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O1[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O1[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I1[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I1[2]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I1[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I1[6]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I1[6]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I1[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O1[14]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O1[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O1[30]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O1[30]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O1[19]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O1[19]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I1[5]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I1[5]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I1[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I1[30]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I1[30]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I1[30]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I1[19]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I1[19]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I1[19]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O1[13]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O1[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I1[13]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I1[13]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I1[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O1[5]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O1[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O1[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O1[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I1[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I1[1]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I1[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O1[4]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O1[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O1[11]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O1[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O1[28]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O1[28]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I1[14]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I1[14]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I1[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x32" "I2[7]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x32" "I2[7]" '(0.6)
defineHierAntennaProp "SRAM2RW32x32" "I2[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.28824 1.24826 0 1.28824 0 0)
("M4" 0.021 0.1516 62.5889 0 0.1516 0 0)
("M5" 0.021 0.1516 69.8033 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O2[18]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O2[18]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O2[7]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O2[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x32" "O2[24]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x32" "O2[24]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.277728 0 0 0.277728 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "A1[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineHierAntennaProp "SRAM2RW32x39" "A1[2]" '(
("M1" 0.0366 0.895918 0 0 0.895918 0 0)
("M2" 0.0366 0.1516 24.477 0 0.1516 0 0)
("M3" 0.0366 0.1516 28.6172 0 0.1516 0 0)
("M4" 0.0366 0.1516 32.7571 0 0.1516 0 0)
("M5" 0.0366 0.1516 36.8968 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O1[24]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O1[24]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I1[24]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW32x39" "I1[24]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O1[23]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O1[23]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I1[23]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW32x39" "I1[23]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O1[22]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O1[22]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I1[22]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW32x39" "I1[22]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O1[21]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O1[21]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I1[21]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineHierAntennaProp "SRAM2RW32x39" "I1[21]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O1[20]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O1[20]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I1[20]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I1[20]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I1[20]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O1[19]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O1[19]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I1[19]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I1[19]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I1[19]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O1[18]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O1[18]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I1[18]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I1[18]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I1[18]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O1[17]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O1[17]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.265273 0 0 0.265273 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I1[17]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I1[17]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I1[17]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O1[16]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O1[16]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I1[16]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I1[16]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I1[16]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O1[15]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O1[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I1[4]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I1[4]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I1[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O2[38]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O2[38]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I2[38]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I2[38]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I2[38]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O2[37]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O2[37]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I2[37]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I2[37]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I2[37]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O2[36]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O2[36]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I2[36]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I2[36]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I2[36]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O2[35]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O2[35]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I2[35]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I2[35]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I2[35]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O2[34]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O2[34]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O2[33]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O2[33]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I2[34]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I2[34]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I2[34]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I2[33]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I2[33]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I2[33]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O2[32]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O2[32]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.265273 0 0 0.265273 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I1[7]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I1[7]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I1[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O1[6]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O1[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I1[6]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I1[6]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I1[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "VSS" '(0 0 0 0 5.49 5.49 5.49 5.49 5.49 5.49)
defineDiodeProtection "SRAM2RW32x39" "VSS" '(0 0 0 0 232.2955 232.2955 232.2955 232.2955 232.2955 232.2955)
defineHierAntennaProp "SRAM2RW32x39" "VSS" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 5.49 3604.65 86.3141 0 3604.65 0 0)
("M6" 5.49 0 0 0 0 0 0)
("M7" 5.49 0 0 0 0 0 0)
("M8" 5.49 0 0 0 0 0 0)
("M9" 5.49 0 0 0 0 0 0)
("MRDL" 5.49 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "CE1" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineDiodeProtection "SRAM2RW32x39" "CE1" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "CE1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0342 0.29968 3.80244 0 0.29968 0 0)
("M5" 0.0342 0.1516 12.5642 0 0.1516 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "A2[4]" '(0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "A2[4]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "A2[4]" '(
("M1" 0.021 0.97657 0 0 0.97657 0 0)
("M2" 0.021 0.1516 46.5003 0 0.1516 0 0)
("M3" 0.021 0.1516 53.7158 0 0.1516 0 0)
("M4" 0.021 0.1516 60.9308 0 0.1516 0 0)
("M5" 0.021 0.1516 68.1454 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O1[7]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O1[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "CSB1" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x39" "CSB1" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "CSB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0366 0.424789 1.92429 0 0.424789 0 0)
("M5" 0.0366 0.1516 13.5297 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "VDD" '(0 0 0 0 3.0816 3.0816 3.0816 3.0816 3.0816 3.0816)
defineDiodeProtection "SRAM2RW32x39" "VDD" '(0 0 0 0 249.2349 249.2349 249.2349 249.2349 249.2349 249.2349)
defineHierAntennaProp "SRAM2RW32x39" "VDD" '(
("M1" 0 0 0 0 0 0 0)
("M2" 0 0 0 0 0 0 0)
("M3" 0 0 0 0 0 0 0)
("M4" 0 0 0 0 0 0 0)
("M5" 3.0816 3604.65 29.5888 0 3604.65 0 0)
("M6" 3.0816 0 0 0 0 0 0)
("M7" 3.0816 0 0 0 0 0 0)
("M8" 3.0816 0 0 0 0 0 0)
("M9" 3.0816 0 0 0 0 0 0)
("MRDL" 3.0816 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I1[31]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I1[31]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I1[31]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O1[31]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O1[31]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I1[32]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I1[32]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I1[32]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O1[32]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O1[32]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I1[33]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I1[33]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I1[33]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O1[33]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O1[33]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.265273 0 0 0.265273 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I1[34]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I1[34]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I1[34]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O1[34]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O1[34]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I1[35]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I1[35]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I1[35]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O1[35]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O1[35]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I1[36]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I1[36]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I1[36]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O1[36]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O1[36]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I1[37]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I1[37]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I1[37]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O1[37]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O1[37]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I1[38]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I1[38]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I1[38]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O1[38]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O1[38]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "OEB2" '(0 0.627 0.627 0.627 0.627 0.627 0.627 0.627 0.627 0.627)
defineDiodeProtection "SRAM2RW32x39" "OEB2" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "OEB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.627 3.44602 0.966023 0 3.44602 0 0)
("M3" 0.627 0.1516 6.46164 0 0.1516 0 0)
("M4" 0.627 0.1516 6.70299 0 0.1516 0 0)
("M5" 0.627 0.1516 6.94431 0 0.1516 0 0)
("M6" 0.627 0 0 0 0 0 0)
("M7" 0.627 0 0 0 0 0 0)
("M8" 0.627 0 0 0 0 0 0)
("M9" 0.627 0 0 0 0 0 0)
("MRDL" 0.627 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "OEB1" '(0 0.627 0.627 0.627 0.627 0.627 0.627 0.627 0.627 0.627)
defineDiodeProtection "SRAM2RW32x39" "OEB1" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "OEB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.627 3.45184 0.966023 0 3.45184 0 0)
("M3" 0.627 0.1516 6.47092 0 0.1516 0 0)
("M4" 0.627 0.1516 6.71227 0 0.1516 0 0)
("M5" 0.627 0.1516 6.95359 0 0.1516 0 0)
("M6" 0.627 0 0 0 0 0 0)
("M7" 0.627 0 0 0 0 0 0)
("M8" 0.627 0 0 0 0 0 0)
("M9" 0.627 0 0 0 0 0 0)
("MRDL" 0.627 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "WEB2" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineDiodeProtection "SRAM2RW32x39" "WEB2" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "WEB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1461 1.56742 1.03833 0 1.56742 0 0)
("M3" 0.1461 0.1516 11.766 0 0.1516 0 0)
("M4" 0.1461 0.1516 12.8028 0 0.1516 0 0)
("M5" 0.1461 0.1516 13.8395 0 0.1516 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "A1[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x39" "A1[0]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "A1[0]" '(
("M1" 0.0366 0.895918 0 0 0.895918 0 0)
("M2" 0.0366 0.1516 24.477 0 0.1516 0 0)
("M3" 0.0366 0.1516 28.6172 0 0.1516 0 0)
("M4" 0.0366 0.1516 32.7571 0 0.1516 0 0)
("M5" 0.0366 0.1516 36.8968 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "A2[3]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x39" "A2[3]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "A2[3]" '(
("M1" 0.0366 0.895918 0 0 0.895918 0 0)
("M2" 0.0366 0.1516 24.477 0 0.1516 0 0)
("M3" 0.0366 0.1516 28.6172 0 0.1516 0 0)
("M4" 0.0366 0.1516 32.7571 0 0.1516 0 0)
("M5" 0.0366 0.1516 36.8968 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "A2[2]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x39" "A2[2]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "A2[2]" '(
("M1" 0.0366 0.895918 0 0 0.895918 0 0)
("M2" 0.0366 0.1516 24.477 0 0.1516 0 0)
("M3" 0.0366 0.1516 28.6172 0 0.1516 0 0)
("M4" 0.0366 0.1516 32.7571 0 0.1516 0 0)
("M5" 0.0366 0.1516 36.8968 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "A2[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x39" "A2[1]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "A2[1]" '(
("M1" 0.0366 0.895918 0 0 0.895918 0 0)
("M2" 0.0366 0.1516 24.477 0 0.1516 0 0)
("M3" 0.0366 0.1516 28.6172 0 0.1516 0 0)
("M4" 0.0366 0.1516 32.7571 0 0.1516 0 0)
("M5" 0.0366 0.1516 36.8968 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "A2[0]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x39" "A2[0]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "A2[0]" '(
("M1" 0.0366 0.895918 0 0 0.895918 0 0)
("M2" 0.0366 0.1516 24.477 0 0.1516 0 0)
("M3" 0.0366 0.1516 28.6172 0 0.1516 0 0)
("M4" 0.0366 0.1516 32.7571 0 0.1516 0 0)
("M5" 0.0366 0.1516 36.8968 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "A1[1]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x39" "A1[1]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "A1[1]" '(
("M1" 0.0366 0.895918 0 0 0.895918 0 0)
("M2" 0.0366 0.1516 24.477 0 0.1516 0 0)
("M3" 0.0366 0.1516 28.6172 0 0.1516 0 0)
("M4" 0.0366 0.1516 32.7571 0 0.1516 0 0)
("M5" 0.0366 0.1516 36.8968 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "CE2" '(0 0 0 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342 0.0342)
defineDiodeProtection "SRAM2RW32x39" "CE2" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "CE2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0342 0.30916 3.47688 0 0.30916 0 0)
("M5" 0.0342 0.1516 12.5158 0 0.1516 0 0)
("M6" 0.0342 0 0 0 0 0 0)
("M7" 0.0342 0 0 0 0 0 0)
("M8" 0.0342 0 0 0 0 0 0)
("M9" 0.0342 0 0 0 0 0 0)
("MRDL" 0.0342 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I1[25]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I1[25]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I1[25]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O1[25]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O1[25]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.265273 0 0 0.265273 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I1[26]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I1[26]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I1[26]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O1[26]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O1[26]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I1[27]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I1[27]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I1[27]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O1[27]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O1[27]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I1[28]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I1[28]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I1[28]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O1[28]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O1[28]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I1[29]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I1[29]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I1[29]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O1[29]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O1[29]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I1[30]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I1[30]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I1[30]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O1[30]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O1[30]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I1[15]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I1[15]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I1[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O1[14]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O1[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I1[14]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I1[14]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I1[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O1[13]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O1[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I1[13]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I1[13]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I1[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O1[12]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O1[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I1[12]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I1[12]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I1[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O1[11]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O1[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I1[11]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I1[11]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I1[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O1[10]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O1[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I1[10]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I1[10]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I1[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O1[9]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O1[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.265273 0 0 0.265273 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I1[9]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I1[9]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I1[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O1[8]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O1[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I1[8]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I1[8]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I1[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "A1[4]" '(0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "A1[4]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "A1[4]" '(
("M1" 0.021 0.97657 0 0 0.97657 0 0)
("M2" 0.021 0.1516 46.5003 0 0.1516 0 0)
("M3" 0.021 0.1516 53.7158 0 0.1516 0 0)
("M4" 0.021 0.1516 60.9308 0 0.1516 0 0)
("M5" 0.021 0.1516 68.1454 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "A1[3]" '(0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x39" "A1[3]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "A1[3]" '(
("M1" 0.0366 0.895918 0 0 0.895918 0 0)
("M2" 0.0366 0.1516 24.477 0 0.1516 0 0)
("M3" 0.0366 0.1516 28.6172 0 0.1516 0 0)
("M4" 0.0366 0.1516 32.7571 0 0.1516 0 0)
("M5" 0.0366 0.1516 36.8968 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O2[4]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O2[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O1[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O1[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I1[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I1[1]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I1[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O1[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O1[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.265273 0 0 0.265273 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I1[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I1[2]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I1[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I1[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I1[0]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I1[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O1[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O1[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I2[1]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I2[1]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I2[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I1[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I1[3]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I1[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O1[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O1[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O2[1]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O2[1]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O2[0]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O2[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.265273 0 0 0.265273 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I2[0]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I2[0]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I2[0]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O2[2]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O2[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O2[3]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O2[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I2[3]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I2[3]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I2[3]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I2[2]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I2[2]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I2[2]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O2[13]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O2[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I2[13]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I2[13]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I2[13]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O2[12]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O2[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I2[12]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I2[12]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I2[12]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O2[11]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O2[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I2[11]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I2[11]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I2[11]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O2[10]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O2[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I2[10]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I2[10]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I2[10]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O2[9]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O2[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I2[9]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I2[9]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I2[9]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O2[8]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O2[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.265273 0 0 0.265273 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I2[8]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I2[8]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I2[8]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O2[7]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O2[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I2[7]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I2[7]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I2[7]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O2[6]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O2[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I2[6]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I2[6]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I2[6]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O2[5]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O2[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I2[4]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I2[4]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I2[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I2[5]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I2[5]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I2[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I2[23]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I2[23]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I2[23]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O2[22]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O2[22]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I2[22]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I2[22]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I2[22]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O2[21]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O2[21]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I2[21]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I2[21]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I2[21]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O2[20]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O2[20]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I2[20]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I2[20]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I2[20]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O2[19]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O2[19]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I2[19]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I2[19]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I2[19]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O2[18]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O2[18]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I2[18]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I2[18]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I2[18]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O2[17]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O2[17]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I2[17]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I2[17]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I2[17]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O2[16]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O2[16]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.265273 0 0 0.265273 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I2[16]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I2[16]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I2[16]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O2[15]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O2[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I2[15]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I2[15]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I2[15]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O2[14]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O2[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I2[14]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I2[14]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I2[14]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I2[32]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I2[32]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I2[32]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O2[31]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O2[31]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I2[31]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I2[31]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I2[31]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O2[30]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O2[30]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I2[30]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I2[30]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I2[30]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O2[29]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O2[29]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I2[29]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I2[29]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I2[29]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O2[28]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O2[28]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I2[28]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I2[28]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I2[28]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O2[27]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O2[27]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I2[27]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I2[27]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I2[27]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O2[26]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O2[26]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I2[26]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I2[26]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I2[26]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O2[25]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O2[25]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I2[25]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I2[25]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I2[25]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O2[24]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O2[24]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.265273 0 0 0.265273 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I2[24]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I2[24]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I2[24]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O2[23]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O2[23]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O1[5]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O1[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "CSB2" '(0 0 0 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366 0.0366)
defineDiodeProtection "SRAM2RW32x39" "CSB2" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "CSB2" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.1516 0 0 0.1516 0 0)
("M4" 0.0366 0.40684 1.96052 0 0.40684 0 0)
("M5" 0.0366 0.1516 13.0755 0 0.1516 0 0)
("M6" 0.0366 0 0 0 0 0 0)
("M7" 0.0366 0 0 0 0 0 0)
("M8" 0.0366 0 0 0 0 0 0)
("M9" 0.0366 0 0 0 0 0 0)
("MRDL" 0.0366 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "WEB1" '(0 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461 0.1461)
defineDiodeProtection "SRAM2RW32x39" "WEB1" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "WEB1" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0.1461 1.56742 1.03833 0 1.56742 0 0)
("M3" 0.1461 0.1516 11.766 0 0.1516 0 0)
("M4" 0.1461 0.1516 12.8028 0 0.1516 0 0)
("M5" 0.1461 0.1516 13.8395 0 0.1516 0 0)
("M6" 0.1461 0 0 0 0 0 0)
("M7" 0.1461 0 0 0 0 0 0)
("M8" 0.1461 0 0 0 0 0 0)
("M9" 0.1461 0 0 0 0 0 0)
("MRDL" 0.1461 0 0 0 0 0 0)
)
defineGateSize "SRAM2RW32x39" "I1[5]" '(0 0 0.021 0.021 0.021 0.021 0.021 0.021 0.021 0.021)
defineDiodeProtection "SRAM2RW32x39" "I1[5]" '(0.6)
defineHierAntennaProp "SRAM2RW32x39" "I1[5]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0.021 1.27792 1.24827 0 1.27792 0 0)
("M4" 0.021 0.1516 62.0975 0 0.1516 0 0)
("M5" 0.021 0.1516 69.312 0 0.1516 0 0)
("M6" 0.021 0 0 0 0 0 0)
("M7" 0.021 0 0 0 0 0 0)
("M8" 0.021 0 0 0 0 0 0)
("M9" 0.021 0 0 0 0 0 0)
("MRDL" 0.021 0 0 0 0 0 0)
)
defineDiodeProtection "SRAM2RW32x39" "O1[4]" '(0 0 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118 0.11118)
defineHierAntennaProp "SRAM2RW32x39" "O1[4]" '(
("M1" 0 0.1516 0 0 0.1516 0 0)
("M2" 0 0.1516 0 0 0.1516 0 0)
("M3" 0 0.264673 0 0 0.264673 0 0)
("M4" 0 0.1516 0 0 0.1516 0 0)
("M5" 0 0.1516 0 0 0.1516 0 0)
("M6" 0 0 0 0 0 0 0)
("M7" 0 0 0 0 0 0 0)
("M8" 0 0 0 0 0 0 0)
("M9" 0 0 0 0 0 0 0)
("MRDL" 0 0 0 0 0 0 0)
)
